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* ppc/xive: Export xive_tctx_word2() helperCédric Le Goater2021-09-291-0/+5
| | | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210901094153.227671-8-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/xive: Export priority_to_ipb() helperCédric Le Goater2021-09-291-0/+11
| | | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210901094153.227671-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* host-utils: introduce uabs64()Luis Pires2021-09-291-0/+8
| | | | | | | | | | | | | Introduce uabs64(), a function that returns the absolute value of a 64-bit int as an unsigned value. This avoids the undefined behavior for common abs implementations, where abs of the most negative value is undefined. Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20210910112624.72748-4-luis.pires@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* host-utils: fix missing zero-extension in divs128Luis Pires2021-09-291-1/+1
| | | | | | | | | | | *plow (lower 64 bits of the dividend) is passed into divs128() as a signed 64-bit integer. When building an __int128_t from it, it must be zero-extended, instead of sign-extended. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Message-Id: <20210910112624.72748-3-luis.pires@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* hw/loader: Restrict PC_ROM_* definitions to hw/i386/pcPhilippe Mathieu-Daudé2021-09-271-6/+0Star
| | | | | | | | | | | The PC_ROM_* definitions are only used by the PC machine, and are irrelevant to the other architectures / machines. Reduce their scope by moving them to hw/i386/pc.c. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210917185949.2244956-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20210921' into stagingRichard Henderson2021-09-242-1/+15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move cpu_signal_handler declaration. Restrict cpu_handle_halt to sysemu. Make do_unaligned_access noreturn. Misc tcg/mips cleanup Misc tcg/sparc cleanup Misc tcg/riscv cleanup # gpg: Signature made Tue 21 Sep 2021 10:47:29 PM EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * remotes/rth/tags/pull-tcg-20210921: tcg/riscv: Remove add with zero on user-only memory access hw/core: Make do_unaligned_access noreturn tcg/sparc: Introduce tcg_out_mov_delay tcg/sparc: Drop inline markers tcg/mips: Drop special alignment for code_gen_buffer tcg/mips: Unset TCG_TARGET_HAS_direct_jump tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr tcg/mips: Drop inline markers accel/tcg: Restrict cpu_handle_halt() to sysemu include/exec: Move cpu_signal_handler declaration Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * hw/core: Make do_unaligned_access noreturnRichard Henderson2021-09-221-1/+2
| | | | | | | | | | | | | | | | | | | | While we may have had some thought of allowing system-mode to return from this hook, we have no guests that require this. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-221-0/+13
| | | | | | | | | | | | | | | | | | | | There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | hw/nvme: fix verification of select field in namespace attachmentNaveen Nagar2021-09-241-0/+5
|/ | | | | | | | | Fix is added to check for reserved value in select field for namespace attachment CC: Minwoo Im <minwoo.im.dev@gmail.com> Signed-off-by: Naveen Nagar <naveen.n1@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
* Merge remote-tracking branch ↵Richard Henderson2021-09-218-61/+165
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/alistair23/tags/pull-riscv-to-apply-20210921' into staging Second RISC-V PR for QEMU 6.2 - ePMP CSR address updates - Convert internal interrupts to use QEMU GPIO lines - SiFive PWM support - Support for RISC-V ACLINT - SiFive PDMA fixes - Update to u-boot instructions for sifive_u - mstatus.SD bug fix for hypervisor extensions - OpenTitan fix for USB dev address # gpg: Signature made Mon 20 Sep 2021 11:52:26 PM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair23/tags/pull-riscv-to-apply-20210921: (21 commits) hw/riscv: opentitan: Correct the USB Dev address target/riscv: csr: Rename HCOUNTEREN_CY and friends target/riscv: Backup/restore mstatus.SD bit when virtual register swapped docs/system/riscv: sifive_u: Update U-Boot instructions hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer hw/dma: sifive_pdma: allow non-multiple transaction size transactions hw/dma: sifive_pdma: claim bit must be set before DMA transactions hw/dma: sifive_pdma: reset Next* registers when Control.claim is set hw/riscv: virt: Add optional ACLINT support to virt machine hw/riscv: virt: Re-factor FDT generation hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT hw/intc: Rename sifive_clint sources to riscv_aclint sources sifive_u: Connect the SiFive PWM device hw/timer: Add SiFive PWM support hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines hw/intc: sifive_clint: Use RISC-V CPU GPIO lines target/riscv: Expose interrupt pending bits as GPIO lines target/riscv: Fix satp write ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel2021-09-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | We extend virt machine to emulate ACLINT devices only when "aclint=on" parameter is passed along with machine name in QEMU command-line. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-5-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-201-18/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | The RISC-V ACLINT is more modular and backward compatible with original SiFive CLINT so instead of duplicating the original SiFive CLINT implementation we upgrade the current SiFive CLINT implementation to RISC-V ACLINT implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-3-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-201-0/+0
| | | | | | | | | | | | | | | | | | | | | | We will be upgrading SiFive CLINT implementation into RISC-V ACLINT implementation so let's first rename the sources. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-2-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-201-1/+13
| | | | | | | | | | | | | | | | Connect the SiFive PWM device and expose it via the device tree. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alistair.francis@wdc.com
| * hw/timer: Add SiFive PWM supportAlistair Francis2021-09-201-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | This is the initial commit of the SiFive PWM timer. This is used by guest software as a timer and is included in the SiFive FU540 SoC. Signed-off-by: Justin Restivo <jrestivo@draper.com> Signed-off-by: Alexandra Clifford <aclifford@draper.com> Signed-off-by: Amanda Strnad <astrnad@draper.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 9f70a210acbfaf0e1ea6ad311ab892ac69134d8b.1631159656.git.alistair.francis@wdc.com
| * hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis2021-09-201-0/+2
| | | | | | | | | | | | | | | | | | | | Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
| * hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 0364190bfa935058a845c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com
| * hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-201-0/+2
| | | | | | | | | | | | | | | | | | | | Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 0a76946981852f5bd15f0c37ab35b253371027a8.1630301632.git.alistair.francis@wdc.com
| * hw/intc: sifive_clint: Use RISC-V CPU GPIO linesAlistair Francis2021-09-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer and soft MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-id: 946e1ef5e268b24084c7ddad84c146de62a56736.1630301632.git.alistair.francis@wdc.com
* | Merge remote-tracking branch ↵Peter Maydell2021-09-211-1/+11
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20210921' into staging target-arm queue: * Optimize codegen for MVE when predication not active * hvf: Add Apple Silicon support * hw/intc: Set GIC maintenance interrupt level to only 0 or 1 * Fix mishandling of MVE FPSCR.LTPSIZE reset for usermode emulator * elf2dmp: Fix coverity nits # gpg: Signature made Tue 21 Sep 2021 16:31:17 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210921: (27 commits) target/arm: Optimize MVE 1op-immediate insns target/arm: Optimize MVE VSLI and VSRI target/arm: Optimize MVE VSHLL and VMOVL target/arm: Optimize MVE VSHL, VSHR immediate forms target/arm: Optimize MVE VMVN target/arm: Optimize MVE VDUP target/arm: Optimize MVE VNEG, VABS target/arm: Optimize MVE arithmetic ops target/arm: Optimize MVE logic ops target/arm: Add TB flag for "MVE insns not predicated" target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration target/arm: Avoid goto_tb if we're trying to exit to the main loop hvf: arm: Add rudimentary PMC support arm: Add Hypervisor.framework build target hvf: arm: Implement PSCI handling hvf: arm: Implement -cpu host arm/hvf: Add a WFI handler hvf: Add Apple Silicon support hvf: Introduce hvf_arch_init() callback hvf: Add execute to dirty log permission bitmap ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | arm/hvf: Add a WFI handlerPeter Collingbourne2021-09-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sleep on WFI until the VTIMER is due but allow ourselves to be woken up on IPI. In this implementation IPI is blocked on the CPU thread at startup and pselect() is used to atomically unblock the signal and begin sleeping. The signal is sent unconditionally so there's no need to worry about races between actually sleeping and the "we think we're sleeping" state. It may lead to an extra wakeup but that's better than missing it entirely. Signed-off-by: Peter Collingbourne <pcc@google.com> Signed-off-by: Alexander Graf <agraf@csgraf.de> Acked-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20210916155404.86958-6-agraf@csgraf.de [agraf: Remove unused 'set' variable, always advance PC on WFX trap, support vm stop / continue operations and cntv offsets] Signed-off-by: Alexander Graf <agraf@csgraf.de> Acked-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hvf: Add Apple Silicon supportAlexander Graf2021-09-201-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With Apple Silicon available to the masses, it's a good time to add support for driving its virtualization extensions from QEMU. This patch adds all necessary architecture specific code to get basic VMs working, including save/restore. Known limitations: - WFI handling is missing (follows in later patch) - No watchpoint/breakpoint support Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210916155404.86958-5-agraf@csgraf.de [PMM: added missing #include] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hvf: Introduce hvf_arch_init() callbackAlexander Graf2021-09-201-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | We will need to install a migration helper for the ARM hvf backend. Let's introduce an arch callback for the overall hvf init chain to do so. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210916155404.86958-4-agraf@csgraf.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/aspeed: Allow machine to set UART defaultPeter Delevoryas2021-09-202-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When you run QEMU with an Aspeed machine and a single serial device using stdio like this: qemu -machine ast2600-evb -drive ... -serial stdio The guest OS can read and write to the UART5 registers at 0x1E784000 and it will receive from stdin and write to stdout. The Aspeed SoC's have a lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on the board design, may be using any of them as the serial console. (See "stdout-path" in a DTS to check which one is chosen). Most boards, including all of those currently defined in hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds some flexibility for different boards without requiring users to change their command-line invocation of QEMU. I tested this doesn't break existing code by booting an AST2500 OpenBMC image and an AST2600 OpenBMC image, each using UART5 as the console. Then I tested switching the default to UART1 and booting an AST2600 OpenBMC image that uses UART1, and that worked too. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210901153615.2746885-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | aspeed: Emulate the AST2600A3Joel Stanley2021-09-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the latest revision of the ASPEED 2600 SoC. As there is no need to model multiple revisions of the same SoC for the moment, update the SCU AST2600 to model the A3 revision instead of the A1 and adapt the AST2600 SoC and machines. Reset values are taken from v8 of the datasheet. Signed-off-by: Joel Stanley <joel@jms.id.au> [ clg: - Introduced an Aspeed "ast2600-a3" SoC class - Commit log update ] Message-Id: <20210629142336.750058-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | watchdog: aspeed: Sanitize control register valuesAndrew Jeffery2021-09-201-0/+1
|/ | | | | | | | | | | | | | | | While some of the critical fields remain the same, there is variation in the definition of the control register across the SoC generations. Reserved regions are adjusted, while in other cases the mutability or behaviour of fields change. Introduce a callback to sanitize the value on writes to ensure model behaviour reflects the hardware. Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210709053107.1829304-2-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* Merge remote-tracking branch ↵Peter Maydell2021-09-161-0/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/trivial-branch-for-6.2-pull-request' into staging Trivial patches pull request 20210916 # gpg: Signature made Thu 16 Sep 2021 15:09:39 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.2-pull-request: target/sparc: Make sparc_cpu_dump_state() static target/avr: Fix compiler errors (-Werror=enum-conversion) hw/vfio: Fix typo in comments intel_iommu: Fix typo in comments target/i386: spelling: occured=>occurred, mininum=>minimum configure: add missing pc-bios/qemu_vga.ndrv symlink in build tree spelling: sytem => system qdev: Complete qdev_init_gpio_out() documentation hw/i386/acpi-build: Fix a typo util: Remove redundant checks in the openpty() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * qdev: Complete qdev_init_gpio_out() documentationPhilippe Mathieu-Daudé2021-09-151-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | qdev_init_gpio_out() states it "creates an array of anonymous output GPIO lines" but doesn't document how this array is released. Add a note that it is automatically free'd in qdev instance_finalize(). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210819142731.2827912-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | Merge remote-tracking branch 'remotes/kraxel/tags/vga-20210916-pull-request' ↵Peter Maydell2021-09-163-2/+9
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging virtio-gpu + ui: fence syncronization. qxl: unbreak live migration. # gpg: Signature made Thu 16 Sep 2021 06:56:03 BST # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20210916-pull-request: virtio-gpu: Add gl_flushed callback ui/gtk-egl: Wait for the draw signal for dmabuf blobs ui: Create sync objects and fences only for blobs ui/egl: Add egl helpers to help with synchronization ui/gtk: Create a common release_dmabuf helper qxl: fix pre-save logic Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | ui/gtk-egl: Wait for the draw signal for dmabuf blobsVivek Kasireddy2021-09-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of immediately drawing and submitting, queue and wait for the draw signal if the dmabuf submitted is a blob. Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Message-Id: <20210914211837.3229977-5-vivek.kasireddy@intel.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ui: Create sync objects and fences only for blobsVivek Kasireddy2021-09-153-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create sync objects and fences only for dmabufs that are blobs. Once a fence is created (after glFlush) and is signalled, graphic_hw_gl_flushed() will be called and virtio-gpu cmd processing will be resumed. Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Message-Id: <20210914211837.3229977-4-vivek.kasireddy@intel.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ui/egl: Add egl helpers to help with synchronizationVivek Kasireddy2021-09-152-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These egl helpers would be used for creating and waiting on a sync object. Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Message-Id: <20210914211837.3229977-3-vivek.kasireddy@intel.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ui/gtk: Create a common release_dmabuf helperVivek Kasireddy2021-09-151-2/+0Star
| |/ | | | | | | | | | | | | | | | | | | | | | | Since the texture release mechanism is same for both gtk-egl and gtk-glarea, move the helper from gtk-egl to common gtk code so that it can be shared by both gtk backends. Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Message-Id: <20210914211837.3229977-2-vivek.kasireddy@intel.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | block: Clarify that @bytes is no limit on *pnumHanna Reitz2021-09-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | .bdrv_co_block_status() implementations are free to return a *pnum that exceeds @bytes, because bdrv_co_block_status() in block/io.c will clamp *pnum as necessary. On the other hand, if drivers' implementations return values for *pnum that are as large as possible, our recently introduced block-status cache will become more effective. So, make a note in block_int.h that @bytes is no upper limit for *pnum. Suggested-by: Eric Blake <eblake@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20210812084148.14458-4-hreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
* | block: block-status cache for data regionsHanna Reitz2021-09-151-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we have attempted before (https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg06451.html, "file-posix: Cache lseek result for data regions"; https://lists.nongnu.org/archive/html/qemu-block/2021-02/msg00934.html, "file-posix: Cache next hole"), this patch seeks to reduce the number of SEEK_DATA/HOLE operations the file-posix driver has to perform. The main difference is that this time it is implemented as part of the general block layer code. The problem we face is that on some filesystems or in some circumstances, SEEK_DATA/HOLE is unreasonably slow. Given the implementation is outside of qemu, there is little we can do about its performance. We have already introduced the want_zero parameter to bdrv_co_block_status() to reduce the number of SEEK_DATA/HOLE calls unless we really want zero information; but sometimes we do want that information, because for files that consist largely of zero areas, special-casing those areas can give large performance boosts. So the real problem is with files that consist largely of data, so that inquiring the block status does not gain us much performance, but where such an inquiry itself takes a lot of time. To address this, we want to cache data regions. Most of the time, when bad performance is reported, it is in places where the image is iterated over from start to end (qemu-img convert or the mirror job), so a simple yet effective solution is to cache only the current data region. (Note that only caching data regions but not zero regions means that returning false information from the cache is not catastrophic: Treating zeroes as data is fine. While we try to invalidate the cache on zero writes and discards, such incongruences may still occur when there are other processes writing to the image.) We only use the cache for nodes without children (i.e. protocol nodes), because that is where the problem is: Drivers that rely on block-status implementations outside of qemu (e.g. SEEK_DATA/HOLE). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/307 Signed-off-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20210812084148.14458-3-hreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> [hreitz: Added `local_file == bs` assertion, as suggested by Vladimir] Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* | block: Drop BDS comment regarding bdrv_append()Hanna Reitz2021-09-151-6/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a comment above the BDS definition stating care must be taken to consider handling newly added fields in bdrv_append(). Actually, this comment should have said "bdrv_swap()" as of 4ddc07cac (nine years ago), and in any case, bdrv_swap() was dropped in 8e419aefa (six years ago). So no such care is necessary anymore. Signed-off-by: Hanna Reitz <hreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20210812084148.14458-2-hreitz@redhat.com>
* | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210914-4' ↵Peter Maydell2021-09-154-30/+43
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Fix translation race condition for user-only. Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ. Fix tcg/arm tcg_out_vec_op signature. Fix tcg/ppc (32bit) build with clang. Remove dupluate TCG_KICK_PERIOD definition. Remove unused tcg_global_reg_new. Restrict cpu_exec_interrupt and its callees to sysemu. Cleanups for tcg/arm. # gpg: Signature made Tue 14 Sep 2021 20:28:35 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210914-4: (43 commits) tcg/arm: More use of the TCGReg enum tcg/arm: More use of the ARMInsn enum tcg/arm: Give enum arm_cond_code_e a typedef and use it tcg/arm: Drop inline markers tcg/arm: Simplify usage of encode_imm tcg/arm: Split out tcg_out_ldstm tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call tcg/arm: Simplify use_armv5t_instructions tcg/arm: Standardize on tcg_out_<branch>_{reg,imm} tcg/arm: Remove fallback definition of __ARM_ARCH accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts user: Remove cpu_get_pic_interrupt() stubs accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu target/rx: Restrict cpu_exec_interrupt() handler to sysemu target/sparc: Restrict cpu_exec_interrupt() handler to sysemu target/sh4: Restrict cpu_exec_interrupt() handler to sysemu target/riscv: Restrict cpu_exec_interrupt() handler to sysemu target/ppc: Restrict cpu_exec_interrupt() handler to sysemu target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemuPhilippe Mathieu-Daudé2021-09-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | All targets call TCGCPUOps::cpu_exec_interrupt() from sysemu code. Move its declaration to restrict it to system emulation. Extend the code guarded. Restrict the static inlined need_replay_interrupt() method to avoid a "defined but not used" warning. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210911165434.531552-24-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * accel/tcg: Rename user-mode do_interrupt hack as fake_user_interruptPhilippe Mathieu-Daudé2021-09-141-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | do_interrupt() is sysemu specific. However due to some X86 specific hack, it is also used in user-mode emulation, which is why it couldn't be restricted to CONFIG_SOFTMMU (see the comment around added in commit 78271684719: "cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"). Keep the hack but rename the handler as fake_user_interrupt() and restrict do_interrupt() to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210911165434.531552-6-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Remove tcg_global_reg_new definesBin Meng2021-09-141-2/+0Star
| | | | | | | | | | | | | | | | | | | | Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"), these tcg_global_reg_new_ macros are not used anywhere. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * accel/tcg: Clear PAGE_WRITE before translationIlya Leoshkevich2021-09-142-16/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | translate_insn() implementations fetch instruction bytes piecemeal, which can cause qemu-user to generate inconsistent translations if another thread modifies them concurrently [1]. Fix by making pages containing translated instruction non-writable right before loading instruction bytes from them. [1] https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00644.html Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20210805204835.158918-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-4/+5
| | | | | | | | | | | | Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | chardev: add some comments about the class methodsMarc-André Lureau2021-09-141-0/+33
| | | | | | | | | | | | Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20210804154848.557328-5-marcandre.lureau@redhat.com>
* | chardev: remove needless class methodMarc-André Lureau2021-09-141-1/+0Star
|/ | | | | | | | | "chr_option_parsed" is only implemented by the "mux" chardev, we can specialize the code there to avoid the needless generic class method. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2021-09-134-1/+70
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20210913-3' into staging target-arm queue: * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command line user-created devices are not plugged into them * Take an exception if PSTATE.IL is set * Support an emulated ITS in the virt board * Add support for kudo-bmc board * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM * cadence_uart: Fix clock handling issues that prevented u-boot from running # gpg: Signature made Mon 13 Sep 2021 21:04:52 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210913-3: (23 commits) hw/arm/mps2.c: Mark internal-only I2C buses as 'full' hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn qdev: Support marking individual buses as 'full' target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn target/arm: Take an exception if PSTATE.IL is set tests/data/acpi/virt: Update IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Add IORT files for ITS hw/intc: GICv3 redistributor ITS processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS initial framework hw/arm: Add support for kudo-bmc board. hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM hw/char: cadence_uart: Log a guest error when device is unclocked or in reset hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/char: cadence_uart: Convert to memop_with_attrs() ops ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * qdev: Support marking individual buses as 'full'Peter Maydell2021-09-131-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default, QEMU will allow devices to be plugged into a bus up to the bus class's device count limit. If the user creates a device on the command line or via the monitor and doesn't explicitly specify the bus to plug it in, QEMU will plug it into the first non-full bus that it finds. This is fine in most cases, but some machines have multiple buses of a given type, some of which are dedicated to on-board devices and some of which have an externally exposed connector for user-pluggable devices. One example is I2C buses. Provide a new function qbus_mark_full() so that a machine model can mark this kind of "internal only" bus as 'full' after it has created all the devices that should be plugged into that bus. The "find a non-full bus" algorithm will then skip the internal-only bus when looking for a place to plug in user-created devices. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210903151435.22379-2-peter.maydell@linaro.org
| * hw/arm/virt: add ITS support in virt GICShashi Mallela2021-09-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Included creation of ITS as part of virt platform GIC initialization. This Emulated ITS model now co-exists with kvm ITS and is enabled in absence of kvm irq kernel support in a platform. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210910143951.92242-9-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc: GICv3 redistributor ITS processingShashi Mallela2021-09-131-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implemented lpi processing at redistributor to get lpi config info from lpi configuration table,determine priority,set pending state in lpi pending table and forward the lpi to cpuif.Added logic to invoke redistributor lpi processing with translated LPI which set/clear LPI from ITS device as part of ITS INT,CLEAR,DISCARD command and GITS_TRANSLATER processing. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210910143951.92242-7-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc: GICv3 ITS Feature enablementShashi Mallela2021-09-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Added properties to enable ITS feature and define qemu system address space memory in gicv3 common,setup distributor and redistributor registers to indicate LPI support. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-6-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc: GICv3 ITS Command processingShashi Mallela2021-09-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added ITS command queue handling for MAPTI,MAPI commands,handled ITS translation which triggers an LPI via INT command as well as write to GITS_TRANSLATER register,defined enum to differentiate between ITS command interrupt trigger and GITS_TRANSLATER based interrupt trigger. Each of these commands make use of other functionalities implemented to get device table entry,collection table entry or interrupt translation table entry required for their processing. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210910143951.92242-5-shashi.mallela@linaro.org [PMM: use INTERRUPT for ItsCmdType enum name to avoid conflict with INT type defined by Windows headers] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-02-05 20:35:09 +0100