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path: root/target-arm/translate-a64.c
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* target-arm: A64: Handle blr lrEdgar E. Iglesias2014-05-011-1/+2
* target-arm: implement WFE/YIELD as a yield for AArch64Rob Herring2014-05-011-0/+6
* target-arm: A64: fix unallocated test of scalar SQXTUNAlex Bennée2014-04-171-1/+1
* target-arm: Implement AArch64 EL1 exception handlingRob Herring2014-04-171-0/+3
* target-arm: A64: Implement DC ZVAPeter Maydell2014-04-171-0/+5
* target-arm: A64: Add assertion that FP access was checkedPeter Maydell2014-04-171-24/+51
* target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN setPeter Maydell2014-04-171-5/+295
* target-arm: Add support for generating exceptions with syndrome informationPeter Maydell2014-04-171-14/+35
* target-arm: Provide correct syndrome information for cpreg access trapsPeter Maydell2014-04-171-1/+7
* target-arm: Split out private-to-target functions into internals.hPeter Maydell2014-04-171-0/+1
* target-arm: Fix A64 Neon MLSPeter Maydell2014-03-241-1/+1
* target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)Alex Bennée2014-03-191-4/+105
* target-arm: A64: Add saturating int ops (SQNEG/SQABS)Alex Bennée2014-03-191-6/+45
* target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée2014-03-171-6/+21
* target-arm: A64: Implement FCVTXNPeter Maydell2014-03-171-1/+19
* target-arm: A64: Implement scalar saturating narrow opsAlex Bennée2014-03-171-7/+28
* target-arm: A64: Move handle_2misc_narrow functionAlex Bennée2014-03-171-90/+90
* target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée2014-03-171-3/+19
* target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categoriesPeter Maydell2014-03-171-2/+78
* target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHLPeter Maydell2014-03-171-0/+132
* target-arm: A64: Implement FRINT*Peter Maydell2014-03-171-3/+42
* target-arm: A64: Implement SRIPeter Maydell2014-03-171-8/+49
* target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée2014-03-171-1/+69
* target-arm: A64: List unsupported shift-imm opcodesPeter Maydell2014-03-171-2/+11
* target-arm: A64: Implement FCVTLPeter Maydell2014-03-171-0/+47
* target-arm: A64: Implement FCVTNPeter Maydell2014-03-171-1/+23
* target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructionsPeter Maydell2014-03-171-19/+169
* target-arm: A64: Implement SHLL, SHLL2Peter Maydell2014-03-171-1/+31
* target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALPPeter Maydell2014-03-171-1/+74
* target-arm: A64: Saturating and narrowing shift opsAlex Bennée2014-03-171-3/+178
* target-arm: A64: Add remaining CLS/Z vector opsAlex Bennée2014-03-171-1/+35
* target-arm: A64: Add FSQRT to C3.6.17 (two misc)Alex Bennée2014-03-171-1/+12
* target-arm: A64: Add last AdvSIMD Integer to FP opsAlex Bennée2014-03-171-9/+123
* target-arm: A64: Fix bug in add_sub_ext handling of rnAlex Bennée2014-03-171-2/+1Star
* target-arm: A64: Implement PMULL instructionPeter Maydell2014-03-171-2/+39
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-2/+2
* target-arm: Fix intptr_t vs tcg_target_longRichard Henderson2014-03-101-1/+1
* target-arm: A64: Implement MSR (immediate) instructionsPeter Maydell2014-02-261-1/+24
* target-arm: A64: Implement WFIPeter Maydell2014-02-261-1/+4
* target-arm: Get MMU index information correct for A64 codePeter Maydell2014-02-261-1/+1
* target-arm: Implement AArch64 CurrentEL sysregPeter Maydell2014-02-261-0/+7
* target-arm: A64: Implement unprivileged load/storePeter Maydell2014-02-201-32/+37
* target-arm: A64: Implement narrowing three-reg-diff operationsPeter Maydell2014-02-201-1/+59
* target-arm: A64: Implement the wide 3-reg-different operationsPeter Maydell2014-02-201-1/+40
* target-arm: A64: Add most remaining three-reg-diff widening opsPeter Maydell2014-02-201-21/+88
* target-arm: A64: Add opcode comments to disas_simd_three_reg_diffPeter Maydell2014-02-201-11/+11
* target-arm: A64: Implement store-exclusive for system modePeter Maydell2014-02-201-6/+62
* target-arm: Remove unnecessary code now read/write fns can't failPeter Maydell2014-02-201-2/+0Star
* target-arm: Split cpreg access checks out from read/write functionsPeter Maydell2014-02-201-0/+11
* target-arm: Log bad system register accesses with LOG_UNIMPPeter Maydell2014-02-201-1/+6
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