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* target-arm/gdbstub64.c: remove useless 'break' statement.Chen Gang2014-04-171-2/+0Star
* target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32Peter Maydell2014-04-174-3/+13
* target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pcPeter Maydell2014-04-171-4/+8
* target-arm: Make Cortex-A15 CBAR read-onlyPeter Maydell2014-04-171-1/+1
* target-arm: Implement CBAR for Cortex-A57Peter Maydell2014-04-175-9/+42
* target-arm: Implement Cortex-A57 implementation-defined system registersPeter Maydell2014-04-171-0/+55
* target-arm: Implement RVBAR registerPeter Maydell2014-04-173-0/+16
* target-arm: Implement AArch64 address translation operationsPeter Maydell2014-04-172-31/+25Star
* target-arm: Implement auxiliary fault status registersPeter Maydell2014-04-171-0/+9
* target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8Peter Maydell2014-04-171-5/+91
* target-arm: Don't expose wildcard ID register definitions for ARMv8Peter Maydell2014-04-171-18/+43
* target-arm: Remove THUMB2EE feature from AArch64 'any' CPUPeter Maydell2014-04-171-1/+0Star
* target-arm: Implement ISR_EL1 registerPeter Maydell2014-04-171-0/+18
* target-arm: Implement AArch64 view of ACTLRPeter Maydell2014-04-171-1/+2
* target-arm: Implement AArch64 view of CONTEXTIDRPeter Maydell2014-04-172-16/+19
* target-arm: Implement AArch64 views of AArch32 ID registersPeter Maydell2014-04-171-29/+44
* target-arm: Add Cortex-A57 processorPeter Maydell2014-04-171-0/+43
* target-arm: Implement ARMv8 MVFR registersPeter Maydell2014-04-175-2/+23
* target-arm: Implement AArch64 EL1 exception handlingRob Herring2014-04-176-0/+143
* target-arm: Move arm_log_exception() into internals.hPeter Maydell2014-04-172-31/+31
* target-arm: Implement AArch64 SPSR_EL1Peter Maydell2014-04-175-11/+40
* target-arm: Implement SP_EL0, SP_EL1Peter Maydell2014-04-176-7/+100
* target-arm: Add AArch64 ELR_EL1 register.Peter Maydell2014-04-174-4/+24
* target-arm: Implement AArch64 views of fault status and data registersRob Herring2014-04-173-18/+29
* target-arm: Use dedicated CPU state fields for ARM946 access bit registersPeter Maydell2014-04-172-10/+16
* target-arm: A64: Implement DC ZVAPeter Maydell2014-04-176-6/+128
* target-arm: Don't mention PMU in debug feature registerPeter Maydell2014-04-171-1/+6
* target-arm: Add v8 mmu translation supportRob Herring2014-04-171-32/+77
* target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1Peter Maydell2014-04-172-1/+40
* target-arm: A64: Add assertion that FP access was checkedPeter Maydell2014-04-172-24/+59
* target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN setPeter Maydell2014-04-175-6/+320
* target-arm: Provide syndrome information for MMU faultsRob Herring2014-04-172-0/+25
* target-arm: Add support for generating exceptions with syndrome informationPeter Maydell2014-04-176-54/+140
* target-arm: Provide correct syndrome information for cpreg access trapsPeter Maydell2014-04-175-7/+184
* target-arm: Define exception record for AArch64 exceptionsPeter Maydell2014-04-173-9/+32
* target-arm: Implement AArch64 DAIF system registerPeter Maydell2014-04-172-1/+21
* target-arm: Split out private-to-target functions into internals.hPeter Maydell2014-04-178-20/+55
* target-arm: Add missing 'static' attributeStefan Weil2014-03-271-1/+1
* target-arm: Fix A64 Neon MLSPeter Maydell2014-03-241-1/+1
* target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)Alex Bennée2014-03-193-10/+284
* target-arm: A64: Add saturating int ops (SQNEG/SQABS)Alex Bennée2014-03-193-12/+75
* target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée2014-03-174-37/+140
* target-arm: A64: Implement FCVTXNPeter Maydell2014-03-173-1/+43
* target-arm: A64: Implement scalar saturating narrow opsAlex Bennée2014-03-171-7/+28
* target-arm: A64: Move handle_2misc_narrow functionAlex Bennée2014-03-171-90/+90
* target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée2014-03-174-42/+195
* target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categoriesPeter Maydell2014-03-171-2/+78
* target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHLPeter Maydell2014-03-171-0/+132
* target-arm: A64: Implement FRINT*Peter Maydell2014-03-171-3/+42
* target-arm: A64: Implement SRIPeter Maydell2014-03-171-8/+49
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