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* target-mips: microMIPS32 R6 Major instructionsYongbok Kim2015-06-261-17/+45
* target-mips: microMIPS32 R6 POOL32{I, C} instructionsYongbok Kim2015-06-261-6/+21
* target-mips: microMIPS32 R6 POOL32F instructionsYongbok Kim2015-06-261-32/+199
* target-mips: microMIPS32 R6 POOL32A{XF} instructionsYongbok Kim2015-06-261-10/+72
* target-mips: microMIPS32 R6 branches and jumpsYongbok Kim2015-06-261-40/+202
* target-mips: add microMIPS32 R6 opcode enumYongbok Kim2015-06-261-16/+103
* target-mips: signal RI for removed instructions in microMIPS R6Yongbok Kim2015-06-261-0/+68
* target-mips: raise RI exceptions when FIR.PS = 0Yongbok Kim2015-06-261-33/+45
* target-mips: rearrange gen_compute_compact_branchYongbok Kim2015-06-261-236/+236
* target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAPYongbok Kim2015-06-261-67/+99
* target-mips: remove an unused argumentYongbok Kim2015-06-261-3/+2Star
* target-mips: add microMIPS TLBINV, TLBINVFYongbok Kim2015-06-261-0/+8
* target-mips: fix {RD, WR}PGPR in microMIPSYongbok Kim2015-06-261-2/+2
* target-mips: convert host to MIPS errno values when requiredLeon Alrae2015-06-261-11/+33
* target-mips: add Unified Hosting Interface (UHI) supportLeon Alrae2015-06-264-21/+394
* target-mips: remove identical code in different branchLeon Alrae2015-06-261-21/+4Star
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
* target-mips: enable XPA and LPA featuresLeon Alrae2015-06-121-6/+10
* target-mips: remove misleading comments in translate_init.cLeon Alrae2015-06-121-9/+0Star
* target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae2015-06-122-0/+227
* target-mips: add CP0.PageGrain.ELPA supportLeon Alrae2015-06-125-12/+42
* target-mips: support Page Frame Number Extension fieldLeon Alrae2015-06-121-6/+26
* target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae2015-06-124-42/+63
* target-mips: correct MFC0 for CP0.EntryLo in MIPS64Leon Alrae2015-06-121-6/+6
* target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae2015-06-115-7/+30
* target-mips: Misaligned memory accesses for MSAYongbok Kim2015-06-113-78/+102
* target-mips: Misaligned memory accesses for R6Yongbok Kim2015-06-112-13/+28
* target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae2015-06-114-156/+208
* target-mips: move group of functions above gen_load_fpr32()Leon Alrae2015-06-111-60/+58Star
* kvm: introduce kvm_arch_msi_data_to_gsiEric Auger2015-06-021-0/+5
* kvm: add support for memory transaction attributesPaolo Bonzini2015-04-301-1/+3
* Merge remote-tracking branch 'remotes/mjt/tags/pull-trivial-patches-2015-03-1...Peter Maydell2015-03-191-1/+1
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| * target-mips: Fix warning from SparseStefan Weil2015-03-191-1/+1
* | target-mips: save cpu state before calling MSA load and store helpersLeon Alrae2015-03-181-0/+2
* | target-mips: fix hflags modified in delay / forbidden slotLeon Alrae2015-03-181-4/+15
* | target-mips: fix CP0.BadVAddr by stopping translation on Address ErrorLeon Alrae2015-03-181-0/+1
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* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-47/+47
* Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2015-03-121-1/+1
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| * kvm: add machine state to kvm_arch_initMarcel Apfelbaum2015-03-111-1/+1
* | Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150311' into stagingPeter Maydell2015-03-116-329/+288Star
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| * | target-mips: add missing MSACSR and restore fp_status and hflagsLeon Alrae2015-03-114-27/+46
| * | target-mips: replace cpu_save/cpu_load with VMStateDescriptionLeon Alrae2015-03-114-317/+257Star
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* / cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost2015-03-101-8/+1Star
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* target-mips: pass 0 instead of -1 as rs in microMIPS LUI instructionLeon Alrae2015-02-131-1/+1
* target-mips: fix broken snapshottingLeon Alrae2015-02-131-2/+4
* target-mips: use CP0EnLo_XI instead of magic numberLeon Alrae2015-02-131-2/+2
* target-mips: ll and lld cause AdEL exception for unaligned addressLeon Alrae2015-02-131-3/+7
* target-mips: fix detection of the end of the page during translationLeon Alrae2015-02-131-1/+4
* target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processorsMaciej W. Rozycki2015-02-131-2/+2
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-131-5/+3Star
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