| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/arm: Implement vector float32 to bfloat16 conversion | Richard Henderson | 2021-06-03 | 1 | -0/+4 |
| * | target/arm: Implement SVE2 bitwise shift immediate | Stephen Long | 2021-05-25 | 1 | -0/+33 |
| * | target/arm: Implement 128-bit ZIP, UZP, TRN | Richard Henderson | 2021-05-25 | 1 | -0/+3 |
| * | target/arm: Implement SVE2 FLOGB | Stephen Long | 2021-05-25 | 1 | -0/+4 |
| * | target/arm: Implement SVE2 FCVTLT | Stephen Long | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Implement SVE2 FCVTNT | Richard Henderson | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Implement SVE2 TBL, TBX | Stephen Long | 2021-05-25 | 1 | -0/+10 |
| * | target/arm: Implement SVE2 complex integer dot product | Richard Henderson | 2021-05-25 | 1 | -0/+10 |
| * | target/arm: Implement SVE2 complex integer multiply-add (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+9 |
| * | target/arm: Implement SVE2 integer multiply long (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Implement SVE2 multiply-add long (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+17 |
| * | target/arm: Implement SVE2 saturating multiply (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Implement SVE2 saturating multiply-add (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+9 |
| * | target/arm: Implement SVE2 saturating multiply-add high (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+14 |
| * | target/arm: Implement SVE2 FMMLA | Stephen Long | 2021-05-25 | 1 | -0/+3 |
| * | target/arm: Implement SVE2 XAR | Richard Henderson | 2021-05-25 | 1 | -0/+4 |
| * | target/arm: Implement SVE2 HISTCNT, HISTSEG | Stephen Long | 2021-05-25 | 1 | -0/+7 |
| * | target/arm: Implement SVE2 RSUBHNB, RSUBHNT | Stephen Long | 2021-05-25 | 1 | -0/+8 |
| * | target/arm: Implement SVE2 SUBHNB, SUBHNT | Stephen Long | 2021-05-25 | 1 | -0/+8 |
| * | target/arm: Implement SVE2 RADDHNB, RADDHNT | Stephen Long | 2021-05-25 | 1 | -0/+8 |
| * | target/arm: Implement SVE2 ADDHNB, ADDHNT | Stephen Long | 2021-05-25 | 1 | -0/+8 |
| * | target/arm: Implement SVE2 complex integer multiply-add | Richard Henderson | 2021-05-25 | 1 | -0/+18 |
| * | target/arm: Implement SVE2 integer multiply-add long | Richard Henderson | 2021-05-25 | 1 | -0/+28 |
| * | target/arm: Implement SVE2 saturating multiply-add long | Richard Henderson | 2021-05-25 | 1 | -0/+14 |
| * | target/arm: Implement SVE2 MATCH, NMATCH | Stephen Long | 2021-05-25 | 1 | -0/+10 |
| * | target/arm: Implement SVE2 bitwise ternary operations | Richard Henderson | 2021-05-25 | 1 | -0/+6 |
| * | target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS | Richard Henderson | 2021-05-25 | 1 | -1/+2 |
| * | target/arm: Implement SVE2 SQSHRN, SQRSHRN | Richard Henderson | 2021-05-25 | 1 | -0/+16 |
| * | target/arm: Implement SVE2 UQSHRN, UQRSHRN | Richard Henderson | 2021-05-25 | 1 | -0/+16 |
| * | target/arm: Implement SVE2 SQSHRUN, SQRSHRUN | Richard Henderson | 2021-05-25 | 1 | -0/+16 |
| * | target/arm: Implement SVE2 SHRN, RSHRN | Richard Henderson | 2021-05-25 | 1 | -0/+16 |
| * | target/arm: Implement SVE2 floating-point pairwise | Stephen Long | 2021-05-25 | 1 | -0/+35 |
| * | target/arm: Implement SVE2 saturating extract narrow | Richard Henderson | 2021-05-25 | 1 | -0/+24 |
| * | target/arm: Implement SVE2 integer add/subtract long with carry | Richard Henderson | 2021-05-25 | 1 | -0/+3 |
| * | target/arm: Implement SVE2 integer absolute difference and accumulate long | Richard Henderson | 2021-05-25 | 1 | -0/+14 |
| * | target/arm: Implement SVE2 complex integer add | Richard Henderson | 2021-05-25 | 1 | -0/+10 |
| * | target/arm: Implement SVE2 bitwise permute | Richard Henderson | 2021-05-25 | 1 | -0/+15 |
| * | target/arm: Implement SVE2 bitwise exclusive-or interleaved | Richard Henderson | 2021-05-25 | 1 | -0/+5 |
| * | target/arm: Implement SVE2 bitwise shift left long | Richard Henderson | 2021-05-25 | 1 | -0/+8 |
| * | target/arm: Implement SVE2 PMULLB, PMULLT | Richard Henderson | 2021-05-25 | 1 | -0/+1 |
| * | target/arm: Implement SVE2 integer multiply long | Richard Henderson | 2021-05-25 | 1 | -0/+15 |
| * | target/arm: Implement SVE2 integer add/subtract wide | Richard Henderson | 2021-05-25 | 1 | -0/+16 |
| * | target/arm: Implement SVE2 integer add/subtract long | Richard Henderson | 2021-05-25 | 1 | -0/+24 |
| * | target/arm: Implement SVE2 saturating add/subtract (predicated) | Richard Henderson | 2021-05-25 | 1 | -0/+54 |
| * | target/arm: Implement SVE2 integer pairwise arithmetic | Richard Henderson | 2021-05-25 | 1 | -0/+45 |
| * | target/arm: Implement SVE2 integer halving add/subtract (predicated) | Richard Henderson | 2021-05-25 | 1 | -0/+54 |
| * | target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) | Richard Henderson | 2021-05-25 | 1 | -0/+54 |
| * | target/arm: Implement SVE2 integer unary operations (predicated) | Richard Henderson | 2021-05-25 | 1 | -0/+13 |
| * | target/arm: Implement SVE2 integer pairwise add and accumulate long | Richard Henderson | 2021-05-25 | 1 | -0/+14 |
| * | arm tcg cpus: Fix Lesser GPL version number | Chetan Pant | 2020-11-15 | 1 | -1/+1 |
