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path: root/target/arm/translate-a64.c
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* target/arm: Use tcg_constant in handle_sysRichard Henderson2022-04-281-22/+9Star
* target/arm: Use tcg_constant in handle_msr_iRichard Henderson2022-04-281-10/+3Star
* target/arm: Use tcg_constant in gen_adc_CCRichard Henderson2022-04-281-13/+13
* target/arm: Use tcg_constant in gen_exception*Richard Henderson2022-04-281-9/+2Star
* target/arm: Use tcg_constant in gen_mte_check*Richard Henderson2022-04-281-8/+2Star
* target/arm: Use tcg_constant in gen_probe_accessRichard Henderson2022-04-281-8/+4Star
* target/arm: Split out gen_rebuild_hflagsRichard Henderson2022-04-221-12/+9Star
* target/arm: Split out set_btype_rawRichard Henderson2022-04-221-13/+12Star
* target/arm: Change DisasContext.thumb to boolRichard Henderson2022-04-221-1/+1
* target/arm: Change DisasContext.aarch64 to boolRichard Henderson2022-04-221-1/+1
* exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson2022-04-201-3/+3
* target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegenPeter Maydell2022-04-011-1/+6
* target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()Wentao_Liang2022-03-021-1/+1
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-081-4/+4
* target/arm: Take an exception if PC is misalignedRichard Henderson2021-12-151-0/+15
* target/arm: Advance pc for arch single-step exceptionRichard Henderson2021-12-151-0/+1
* target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insnRichard Henderson2021-12-151-3/+4
* target/arm: Drop checks for singlestep_enabledRichard Henderson2021-10-161-8/+2Star
* tcg: Expand MO_SIZE to 3 bitsRichard Henderson2021-10-061-1/+1
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-1/+1
* target/arm: Merge disas_a64_insn into aarch64_tr_translate_insnRichard Henderson2021-09-131-115/+109Star
* target/arm: Take an exception if PSTATE.IL is setPeter Maydell2021-09-131-0/+11
* accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-25/+0Star
* target/arm: Use translator_use_goto_tb for aarch64Richard Henderson2021-07-091-20/+5Star
* tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé2021-07-091-1/+0Star
* target/arm: Use dup_const() instead of bitfield_replicate()Peter Maydell2021-07-021-1/+1
* target/arm: Use asimd_imm_const for A64 decodePeter Maydell2021-07-021-79/+7Star
* target/arm: Improve vector REVRichard Henderson2021-06-291-4/+2Star
* target/arm: Improve REV32Richard Henderson2021-06-291-13/+4Star
* tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64Richard Henderson2021-06-291-5/+7
* target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16Richard Henderson2021-06-151-30/+48
* target/arm: Remove fprintf from disas_simd_mod_immRichard Henderson2021-06-151-1/+0Star
* target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16Richard Henderson2021-06-151-2/+2
* target/arm: Implement bfloat widening fma (indexed)Richard Henderson2021-06-031-1/+14
* target/arm: Implement bfloat widening fma (vector)Richard Henderson2021-06-031-4/+9
* target/arm: Implement bfloat16 matrix multiply accumulateRichard Henderson2021-06-031-0/+10
* target/arm: Implement bfloat16 dot product (indexed)Richard Henderson2021-06-031-9/+32
* target/arm: Implement bfloat16 dot product (vector)Richard Henderson2021-06-031-0/+20
* target/arm: Implement vector float32 to bfloat16 conversionRichard Henderson2021-06-031-0/+17
* target/arm: Implement scalar float32 to bfloat16 conversionRichard Henderson2021-06-031-0/+19
* target/arm: Unify unallocated path in disas_fp_1srcRichard Henderson2021-06-031-9/+6Star
* target/arm: Mark LDS{MIN,MAX} as signed operationsRichard Henderson2021-06-031-3/+10
* target/arm: Implement integer matrix multiply accumulateRichard Henderson2021-05-251-0/+18
* target/arm: Implement aarch64 SUDOT, USDOTRichard Henderson2021-05-251-0/+25
* target/arm: Pass separate addend to FCMLA helpersRichard Henderson2021-05-251-5/+23
* target/arm: Pass separate addend to {U, S}DOT helpersRichard Henderson2021-05-251-2/+13
* target/arm: Implement SVE2 XARRichard Henderson2021-05-251-21/+4Star
* target/arm: Share unallocated_encoding() and gen_exception_insn()Peter Maydell2021-05-101-15/+0Star
* target/arm: Enforce alignment for aa64 vector LDn/STn (single)Richard Henderson2021-04-301-4/+5
* target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)Richard Henderson2021-04-301-4/+11
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-15 22:30:12 +0100