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path: root/target/arm/translate-a64.c
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* target/arm: Remove default_exception_elRichard Henderson2022-06-101-5/+0Star
* target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_ELRichard Henderson2022-06-101-1/+0Star
* target/arm: Introduce gen_exception_insnRichard Henderson2022-06-101-9/+6Star
* target/arm: Rename gen_exception_insn to gen_exception_insn_elRichard Henderson2022-06-101-18/+18
* target/arm: Add coproc parameter to syn_fp_access_trapRichard Henderson2022-06-101-1/+2
* target/arm: Rename TBFLAG_A64 ZCR_LEN to VLRichard Henderson2022-06-081-1/+1
* target/arm: Remove aa64_sve check from before disas_sveRichard Henderson2022-05-301-1/+1
* target/arm: Drop unsupported_encoding() macroPeter Maydell2022-05-191-4/+4
* target/arm: Implement FEAT_IDSTPeter Maydell2022-05-191-2/+26
* target/arm: Enable FEAT_DGH for -cpu maxRichard Henderson2022-05-091-0/+1
* target/arm: Implement ESB instructionRichard Henderson2022-05-091-0/+17
* target/arm: Avoid bare abort() or assert(0)Richard Henderson2022-05-051-2/+2
* target/arm: Reorg ARMCPRegInfo type field bitsRichard Henderson2022-05-051-2/+4
* target/arm: Split out cpregs.hRichard Henderson2022-05-051-3/+1Star
* target/arm: Use tcg_constant in balance of translate-a64.cRichard Henderson2022-04-281-12/+8Star
* target/arm: Use tcg_constant in 2misc expandersRichard Henderson2022-04-281-30/+10Star
* target/arm: Use tcg_constant in simd fp/int conversionRichard Henderson2022-04-281-20/+6Star
* target/arm: Use tcg_constant in simd shift expandersRichard Henderson2022-04-281-16/+5Star
* target/arm: Use tcg_constant in disas_fp*Richard Henderson2022-04-281-16/+7Star
* target/arm: Use tcg_constant in disas_data_proc_2srcRichard Henderson2022-04-281-7/+5Star
* target/arm: Use tcg_constant in handle_{rev16,crc32}Richard Henderson2022-04-281-5/+2Star
* target/arm: Use tcg_constant in disas_cond_selectRichard Henderson2022-04-281-2/+1Star
* target/arm: Use tcg_constant in shift_reg_immRichard Henderson2022-04-281-5/+1Star
* target/arm: Use tcg_constant in disas_movw_immRichard Henderson2022-04-281-4/+1Star
* target/arm: Use tcg_constant in disas_add_sum_imm*Richard Henderson2022-04-281-8/+4Star
* target/arm: Use tcg_constant in disas_ldst_*Richard Henderson2022-04-281-6/+3Star
* target/arm: Use tcg_constant in disas_ld_litRichard Henderson2022-04-281-2/+1Star
* target/arm: Use tcg_constant in gen_compare_and_swap_pairRichard Henderson2022-04-281-4/+2Star
* target/arm: Use tcg_constant in disas_excRichard Henderson2022-04-281-4/+1Star
* target/arm: Use tcg_constant in handle_sysRichard Henderson2022-04-281-22/+9Star
* target/arm: Use tcg_constant in handle_msr_iRichard Henderson2022-04-281-10/+3Star
* target/arm: Use tcg_constant in gen_adc_CCRichard Henderson2022-04-281-13/+13
* target/arm: Use tcg_constant in gen_exception*Richard Henderson2022-04-281-9/+2Star
* target/arm: Use tcg_constant in gen_mte_check*Richard Henderson2022-04-281-8/+2Star
* target/arm: Use tcg_constant in gen_probe_accessRichard Henderson2022-04-281-8/+4Star
* target/arm: Split out gen_rebuild_hflagsRichard Henderson2022-04-221-12/+9Star
* target/arm: Split out set_btype_rawRichard Henderson2022-04-221-13/+12Star
* target/arm: Change DisasContext.thumb to boolRichard Henderson2022-04-221-1/+1
* target/arm: Change DisasContext.aarch64 to boolRichard Henderson2022-04-221-1/+1
* exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson2022-04-201-3/+3
* target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegenPeter Maydell2022-04-011-1/+6
* target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()Wentao_Liang2022-03-021-1/+1
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-081-4/+4
* target/arm: Take an exception if PC is misalignedRichard Henderson2021-12-151-0/+15
* target/arm: Advance pc for arch single-step exceptionRichard Henderson2021-12-151-0/+1
* target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insnRichard Henderson2021-12-151-3/+4
* target/arm: Drop checks for singlestep_enabledRichard Henderson2021-10-161-8/+2Star
* tcg: Expand MO_SIZE to 3 bitsRichard Henderson2021-10-061-1/+1
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-1/+1
* target/arm: Merge disas_a64_insn into aarch64_tr_translate_insnRichard Henderson2021-09-131-115/+109Star