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* target/mips: Rename MMI-related functionsAleksandar Markovic2018-11-171-16/+16
| | | | | | | | Rename MMI-related functions. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Rename MMI-related opcodesAleksandar Markovic2018-11-171-236/+236
| | | | | | | | Rename MMI-related opcodes. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Rename MMI-related masksAleksandar Markovic2018-11-171-10/+10
| | | | | | | | Rename MMI-related masks. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Guard check_insn with INSN_R5900 checkFredrik Noring2018-11-171-3/+6
| | | | | | | | | Explicitely mark handling of PREF instruction for R5900 as treating the same as NOP. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Guard check_insn_opc_user_only with INSN_R5900 checkFredrik Noring2018-11-171-4/+12
| | | | | | | | | Avoid using check_opc_user_only() as a decision making code wrt various architectures. Use ctx->insn_flags checks instead. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Fix decoding mechanism of special R5900 opcodesFredrik Noring2018-11-171-4/+50
| | | | | | | | | | MOVN, MOVZ, MFHI, MFLO, MTHI, MTLO, MULT, MULTU, DIV, DIVU, DMULT, DMULTU, DDIV, DDIVU and JR are decoded in decode_opc_special_tx79 instead of the generic decode_opc_special_legacy. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1Fredrik Noring2018-11-171-6/+59
| | | | | | | | | DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic gen_muldiv. Signed-off-by: Fredrik Noring <noring@nocrew.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1Fredrik Noring2018-11-171-11/+40
| | | | | | | | | MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of the generic gen_HILO. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Amend MXU ASE overview noteAleksandar Markovic2018-10-291-10/+74
| | | | | | | | Add prefix, suffix, operation descriptions, and other corrections and amendments to the comment that describes MXU ASE. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Move MXU_EN check one level higherAleksandar Markovic2018-10-291-271/+238Star
| | | | | | | | Move MXU_EN check to the main MXU decoding function, to avoid code repetition. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add emulation of MXU instructions S32LDD and S32LDDRCraig Janeczek2018-10-291-7/+47
| | | | | | | | Add support for emulating the S32LDD and S32LDDR MXU instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSUCraig Janeczek2018-10-291-7/+94
| | | | | | | | Adds support for emulating the Q8MUL and Q8MULSU MXU instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add emulation of MXU instruction D16MACCraig Janeczek2018-10-291-3/+87
| | | | | | | | Add support for emulating the D16MAC MXU instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add emulation of MXU instruction D16MULCraig Janeczek2018-10-291-3/+63
| | | | | | | | Add support for emulating the D16MUL MXU instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add emulation of MXU instruction S8LDDCraig Janeczek2018-10-291-3/+87
| | | | | | | | Add support for emulating the S8LDD MXU instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switchAleksandar Markovic2018-10-291-18/+23
| | | | | | | | Move MUL, S32M2I, S32I2M handling out of switch. These are all instructions that do not depend on MXU_EN flag of MXU_CR. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add emulation of MXU instructions S32I2M and S32M2ICraig Janeczek2018-10-291-6/+85
| | | | | | | | | | | Add support for emulating the S32I2M and S32M2I MXU instructions. This commit also contains utility functions for reading/writing to MXU registers. This is required for overall MXU instruction support. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add emulation of non-MXU MULL within MXU decoding engineCraig Janeczek2018-10-291-1/+18
| | | | | | | | Add emulation of non-MXU MULL within MXU decoding engine. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add bit encoding for MXU operand getting pattern 'optn3'Craig Janeczek2018-10-291-0/+10
| | | | | | | | Add bit encoding for MXU operand getting pattern 'optn3'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add bit encoding for MXU operand getting pattern 'optn2'Craig Janeczek2018-10-291-0/+6
| | | | | | | | Add bit encoding for MXU operand getting pattern 'optn2'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'Aleksandar Markovic2018-10-291-0/+6
| | | | | | | Add bit encoding for MXU execute 2-bit add/subtract pattern 'eptn2'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'Craig Janeczek2018-10-291-0/+6
| | | | | | | | | Add bit encoding for MXU accumulate add/subtract 2-bit pattern 'aptn2'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'Aleksandar Markovic2018-10-291-0/+6
| | | | | | | | Add bit encoding for MXU accumulate add/subtract 1-bit pattern 'aptn1'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add MXU decoding engineAleksandar Markovic2018-10-291-2/+1141
| | | | | | | | | | Add MXU decoding engine: add handlers for all instruction pools, and main decode handler. The handlers, for now, for the purpose of this patch, contain only sceleton in the form of a single switch statement. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add and integrate MXU decoding engine placeholderAleksandar Markovic2018-10-291-0/+8
| | | | | | | | Provide the placeholder and add the invocation logic for MXU decoding engine. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Amend MXU instruction opcodesAleksandar Markovic2018-10-291-91/+69Star
| | | | | | | | | Amend MXU instruction opcodes. Pool04 is actually only instruction OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit subfield 'aptn1'. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Introduce MXU registersCraig Janeczek2018-10-291-0/+20
| | | | | | | | | | Define and initialize the 16 MXU registers - 15 general computational register, and 1 control register). There is also a zero register, but it does not have any corresponding variable. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder casesAleksandar Markovic2018-10-291-0/+2
| | | | | | | Coverity found two fallthroughs that miss break statement. Fix them. Revieved-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Implement emulation of nanoMIPS EVA instructionsDimitrije Nikolic2018-10-251-0/+128
| | | | | | | | | Implement emulation of nanoMIPS EVA instructions. They are all part of P.LS.E0 instruction pool, or one of its subpools. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add nanoMIPS CRC32 instruction poolAleksandar Markovic2018-10-251-0/+10
| | | | | | | Add nanoMIPS CRC32 instruction pool. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Fix decoding of ALIGN and DALIGN instructionsAleksandar Markovic2018-10-241-8/+32
| | | | | | | | Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to allow paremeter 'bp' to occupy two and three bits, respectively. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Fix the title of translate.cAleksandar Markovic2018-10-241-1/+1
| | | | | | | | Replace MIPS32 with MIPS, since the file covers all generations of MIPS architectures. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user onlyFredrik Noring2018-10-241-1/+22
| | | | | | | | | | | | | | | | | | | The Linux kernel traps certain reserved instruction exceptions to emulate the corresponding instructions. QEMU plays the role of the kernel in user mode, so those traps are emulated by accepting the instructions. This change adds the function check_insn_opc_user_only to signal a reserved instruction exception for flagged CPUs in QEMU system mode. The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not implemented in R5900 hardware. They are trapped and emulated by the Linux kernel and, accordingly, therefore QEMU user only instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IVFredrik Noring2018-10-241-2/+3
| | | | | | | | | | The R5900 is taken to be MIPS III with certain modifications. From MIPS IV it implements the instructions MOVN, MOVZ and PREF. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Support R5900 DIV1 and DIVU1 instructionsFredrik Noring2018-10-241-3/+9
| | | | | | | | Add support for DIV1 and DIVU1 instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructionsFredrik Noring2018-10-241-6/+17
| | | | | | | | Add support for MFLO1, MTLO1, MFHI1 and MTHI1 instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Support R5900 three-operand MULT1 and MULTU1 instructionsFredrik Noring2018-10-241-3/+14
| | | | | | | | Add support for MULT1 and MULTU1 instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Support R5900 three-operand MULT and MULTU instructionsFredrik Noring2018-10-241-0/+74
| | | | | | | | | | | | | | | | The three-operand MULT and MULTU are the only R5900-specific instructions emitted by GCC 7.3. The R5900 also implements the three- operand MADD and MADDU instructions, but they are omitted in QEMU for now since they are absent in programs compiled by current GCC versions. Likewise, the R5900-specific pipeline 1 instruction variants MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1 are omitted here as well. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add a placeholder for R5900 MMI3 instruction subclassFredrik Noring2018-10-241-1/+30
| | | | | | | | Add a placeholder for MMI3 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add a placeholder for R5900 MMI2 instruction subclassFredrik Noring2018-10-241-1/+39
| | | | | | | | Add a placeholder for MMI2 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add a placeholder for R5900 MMI1 instruction subclassFredrik Noring2018-10-241-1/+35
| | | | | | | | Add a placeholder for MM1 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add a placeholder for R5900 MMI0 instruction subclassFredrik Noring2018-10-241-1/+42
| | | | | | | | Add a placeholder for MMI0 subclass. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add a placeholder for R5900 MMI instruction classFredrik Noring2018-10-241-1/+44
| | | | | | | | | Add a placeholder for MMI class. This is the main palceholder for MMI ASE. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add a placeholder for R5900 LQFredrik Noring2018-10-241-2/+11
| | | | | | | | Add a placeholder for LQ instruction. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWRFredrik Noring2018-10-241-1/+52
| | | | | | | | Add placeholder for SQ instruction, handle RDHWR. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Define R5900 MMI3 opcode constantsFredrik Noring2018-10-241-0/+39
| | | | | | Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Define R5900 MMI2 opcode constantsFredrik Noring2018-10-241-0/+48
| | | | | | Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Define R5900 MMI1 opcode constantsFredrik Noring2018-10-241-0/+44
| | | | | | Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Define R5900 MMI0 opcode constantsFredrik Noring2018-10-241-0/+51
| | | | | | | | Add definition of MI0 opcodes. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constantsFredrik Noring2018-10-241-0/+51
| | | | | | | | | Define MMI0, MMI1, MMI2, MMI3 subclass opcodes, and other opcodes of instructions in MMI class. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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