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* | target/mips: Clean up handling of CP0 register 6Aleksandar Markovic2019-08-291-28/+28
* | target/mips: Clean up handling of CP0 register 5Aleksandar Markovic2019-08-291-32/+32
* | target/mips: Clean up handling of CP0 register 4Aleksandar Markovic2019-08-291-16/+20
* | target/mips: Clean up handling of CP0 register 3Aleksandar Markovic2019-08-291-10/+10
* | target/mips: Clean up handling of CP0 register 2Aleksandar Markovic2019-08-291-32/+32
* | target/mips: Clean up handling of CP0 register 1Aleksandar Markovic2019-08-291-32/+32
* | target/mips: Clean up handling of CP0 register 0Aleksandar Markovic2019-08-291-20/+20
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* icount: remove unnecessary gen_io_end callsPavel Dovgalyuk2019-08-201-11/+0Star
* target/mips: Style improvements in translate.cAleksandar Markovic2019-08-191-380/+393
* target/mips: Add 'fall through' comments for handling nanoMips' SHXS, SWXSAleksandar Markovic2019-07-221-0/+2
* target/mips: Add missing 'break' for certain cases of MTTR handlingAleksandar Markovic2019-07-151-0/+2
* target/mips: Add missing 'break' for certain cases of MFTR handlingAleksandar Markovic2019-07-151-0/+2
* target/mips: Add missing 'break' for a case of MTHC0 handlingAleksandar Markovic2019-07-151-0/+1
* target/mips: Correct comments in translate.cAleksandar Markovic2019-07-021-183/+314
* target/mips: Fix if-else-switch-case arms checkpatch errors in translate.cAleksandar Markovic2019-06-211-72/+133
* target/mips: Fix some space checkpatch errors in translate.cAleksandar Markovic2019-06-211-118/+122
* target/mips: Use env_cpu, env_archcpuRichard Henderson2019-06-101-2/+1Star
* target/mips: Add emulation of MMI instruction PCPYUDMateja Marjanovic2019-06-011-1/+42
* target/mips: Add emulation of MMI instruction PCPYLDMateja Marjanovic2019-06-011-1/+42
* target/mips: Add emulation of MMI instruction PCPYHMateja Marjanovic2019-06-011-1/+65
* Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-280519-2...Peter Maydell2019-05-281-1/+9
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| * target/mips: only build mips-semi for softmmuAlex Bennée2019-05-281-0/+8
| * semihosting: move semihosting configuration into its own directoryAlex Bennée2019-05-281-1/+1
* | target/mips: Refactor and fix INSERT.<B|H|W|D> instructionsMateja Marjanovic2019-05-261-1/+18
* | target/mips: Refactor and fix COPY_U.<B|H|W> instructionsMateja Marjanovic2019-05-261-1/+20
* | target/mips: Refactor and fix COPY_S.<B|H|W|D> instructionsMateja Marjanovic2019-05-261-1/+18
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* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-40/+40
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-181-0/+1
* target/mips: Preparing for adding MMI instructionsMateja Marjanovic2019-02-271-2/+41
* target/mips: reimplement SC instruction emulation and use cmpxchgLeon Alrae2019-02-141-81/+42Star
* target/mips: compare virtual addresses in LL/SC sequenceLeon Alrae2019-02-141-2/+2
* target/mips: nanoMIPS: Fix branch handlingStefan Markovic2019-01-241-0/+12
* target/mips: Extend gen_scwp() functionality to support EVAAleksandar Markovic2019-01-241-4/+6
* target/mips: Correct the second argument type of cpu_supports_isa()Aleksandar Markovic2019-01-241-1/+1
* target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbersAleksandar Markovic2019-01-241-13/+13
* target/mips: nanoMIPS: Remove an unused macroAleksandar Markovic2019-01-241-1/+0Star
* target/mips: nanoMIPS: Remove duplicate macro definitionsAleksandar Markovic2019-01-241-10/+0Star
* target/mips: Introduce 32 R5900 multimedia registersFredrik Noring2019-01-181-0/+16
* target/mips: Rename 'rn' to 'register_name'Aleksandar Markovic2019-01-181-426/+432
* target/mips: Amend preprocessor constants for CP0 registersAleksandar Markovic2019-01-181-138/+138
* target/mips: Provide R/W access to SAARI and SAAR CP0 registersYongbok Kim2019-01-181-4/+62
* target/mips: Use preprocessor constants for 32 major CP0 registersAleksandar Markovic2019-01-181-136/+136
* avoid TABs in files that only contain a fewPaolo Bonzini2019-01-111-1/+1
* target/mips: Support R5900 three-operand MADD1 and MADDU1 instructionsFredrik Noring2019-01-031-3/+9
* target/mips: Support R5900 three-operand MADD and MADDU instructionsPhilippe Mathieu-Daudé2019-01-031-5/+53
* target/mips: MXU: Add handler for an align instructionAleksandar Markovic2019-01-031-3/+194
* target/mips: MXU: Add handlers for max/min instructionsAleksandar Markovic2019-01-031-21/+279
* target/mips: MXU: Add handlers for logic instructionsAleksandar Markovic2019-01-031-34/+205
* target/mips: MXU: Improve the comment containing MXU overviewAleksandar Markovic2019-01-031-30/+44
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