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path: root/target/mips/translate.h
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* target/mips/translate: Make gen_rdhwr() publicPhilippe Mathieu-Daudé2021-03-131-0/+2
* target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetreePhilippe Mathieu-Daudé2021-03-131-0/+4
* target/mips: Introduce mxu_translate_init() helperPhilippe Mathieu-Daudé2021-03-131-0/+1
* target/mips: Simplify decode_opc_mxu() ifdef'ryPhilippe Mathieu-Daudé2021-03-131-0/+3
* target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpersPhilippe Mathieu-Daudé2021-02-211-0/+4
* target/mips: Promote 128-bit multimedia registers as global onesPhilippe Mathieu-Daudé2021-02-211-0/+3
* target/mips: Make cpu_HI/LO registers publicPhilippe Mathieu-Daudé2021-02-211-0/+1
* target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodesPhilippe Mathieu-Daudé2021-01-141-0/+1
* target/mips: Extract LSA/DLSA translation generatorsPhilippe Mathieu-Daudé2021-01-141-0/+5
* target/mips: Use decode_ase_msa() generated from decodetreePhilippe Mathieu-Daudé2021-01-141-12/+0Star
* target/mips: Introduce decode tree bindings for MSA ASEPhilippe Mathieu-Daudé2021-01-141-0/+3
* target/mips: Declare gen_msa/_branch() in 'translate.h'Philippe Mathieu-Daudé2021-01-141-0/+2
* target/mips: Extract msa_translate_init() from mips_tcg_init()Philippe Mathieu-Daudé2021-01-141-0/+3
* target/mips/translate: Expose check_mips_64() to 32-bit modePhilippe Mathieu-Daudé2021-01-141-2/+0Star
* target/mips: Extract FPU specific definitions to translate.hPhilippe Mathieu-Daudé2021-01-141-0/+71
* target/mips: Declare generic FPU / Coprocessor functions in translate.hPhilippe Mathieu-Daudé2021-01-141-0/+12
* target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instructionPhilippe Mathieu-Daudé2021-01-141-0/+1
* target/mips/translate: Add declarations for generic codePhilippe Mathieu-Daudé2021-01-141-0/+43
* target/mips/translate: Extract DisasContext structurePhilippe Mathieu-Daudé2021-01-141-0/+50
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 14:06:46 +0100