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* softfloat: Name compare relation enumRichard Henderson2020-05-191-2/+2
* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2020-03-192-5/+5
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| * cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-182-5/+5
* | gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-172-2/+2
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* cpu: Use cpu_class_set_parent_reset()Greg Kurz2020-01-241-2/+1Star
* Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20200116' into stagingPeter Maydell2020-01-171-1/+1
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| * target/openrisc: Fix FPCSR mask to allow setting DZFStafford Horne2020-01-171-1/+1
* | tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
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* target/openrisc: fetch code with translator_ldEmilio G. Cota2019-10-281-1/+1
* target/openrisc: Update cpu "any" to v1.3Richard Henderson2019-09-041-1/+1
* target/openrisc: Implement l.adrpRichard Henderson2019-09-043-0/+16
* target/openrisc: Implement move to/from FPCSRRichard Henderson2019-09-045-5/+38
* target/openrisc: Implement unordered fp comparisonsRichard Henderson2019-09-045-0/+145
* target/openrisc: Add support for ORFPX64A32Richard Henderson2019-09-046-3/+332
* target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson2019-09-042-50/+36Star
* target/openrisc: Fix lf.ftoi.sRichard Henderson2019-09-041-1/+1
* target/openrisc: Add VR2 and AVR special processor registersRichard Henderson2019-09-043-6/+19
* target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu initRichard Henderson2019-09-043-13/+22
* target/openrisc: Make VR and PPC read-onlyRichard Henderson2019-09-042-12/+1Star
* target/openrisc: Cache R0 in DisasContextRichard Henderson2019-09-041-7/+12
* target/openrisc: Replace cpu register array with a functionRichard Henderson2019-09-041-97/+116
* target/openrisc: Add DisasContext parameter to check_r0_writeRichard Henderson2019-09-041-47/+49
* tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2019-09-031-2/+2
* hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster2019-08-211-1/+1
* Include hw/boards.h a bit lessMarkus Armbruster2019-08-161-1/+0Star
* Include hw/hw.h exactly where neededMarkus Armbruster2019-08-161-1/+0Star
* migration: Move the VMStateDescription typedef to typedefs.hMarkus Armbruster2019-08-161-1/+1
* general: Replace global smp variables with smp machine propertiesLike Xu2019-07-051-1/+5
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-129-9/+0Star
* cpu: Remove CPU_COMMONRichard Henderson2019-06-101-2/+0Star
* cpu: Introduce CPUNegativeOffsetStateRichard Henderson2019-06-101-1/+1
* cpu: Introduce cpu_set_cpustate_pointersRichard Henderson2019-06-101-2/+1Star
* cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson2019-06-101-1/+0Star
* target/openrisc: Use env_cpu, env_archcpuRichard Henderson2019-06-103-12/+6Star
* cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2019-06-101-2/+0Star
* cpu: Define ArchCPURichard Henderson2019-06-101-0/+1
* cpu: Define CPUArchState with typedefRichard Henderson2019-06-101-2/+2
* tcg: Split out target/arch/cpu-param.hRichard Henderson2019-06-102-11/+20
* tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson2019-05-101-6/+0Star
* target/openrisc: Convert to CPUClass::tlb_fillRichard Henderson2019-05-103-36/+39
* target/openrisc: Fix LGPL information in the file headersThomas Huth2019-05-088-8/+8
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* disas: Rename include/disas/bfd.h back to include/disas/dis-asm.hMarkus Armbruster2019-04-181-1/+1
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-182-8/+6Star
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-182-11/+6Star
* target/openrisc: Fix LGPL version numberThomas Huth2019-01-307-7/+7
* vmstate: constify VMStateFieldMarc-André Lureau2018-11-271-2/+3
* decodetree: Remove "insn" argument from trans_* expandersRichard Henderson2018-10-312-112/+111Star
* target/openrisc: Fix writes to interrupt mask registerStafford Horne2018-07-031-1/+1
* target/openrisc: Fix delay slot exception flag to match specStafford Horne2018-07-031-7/+12
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