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* target/riscv: Fix checks in hmode/hmode32Weiwei Li2022-09-072-7/+7
* target/riscv: Add check for csrs existed with U extensionWeiwei Li2022-09-071-3/+21
* target/riscv: Fix checkpatch warning may triggered in csr_ops tableWeiwei Li2022-09-071-207/+234
* target/riscv: H extension depends on I extensionWeiwei Li2022-09-071-0/+6
* target/riscv: Add check for supported privilege mode combinationsWeiwei Li2022-09-071-0/+6
* target/riscv: move zmmul out of the experimental propertiesWeiwei Li2022-09-071-1/+2
* target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot2022-09-072-5/+22
* target/riscv: Force disable extensions if priv spec version does not matchAnup Patel2022-09-071-56/+94
* target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel2022-09-073-6/+296
* target/riscv: Make translator stop before the end of a pageRichard Henderson2022-09-061-4/+13
* target/riscv: Add MAX_INSN_LEN and insn_lenRichard Henderson2022-09-061-1/+9
* accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson2022-09-061-2/+3
* meson: remove dead codePaolo Bonzini2022-09-011-2/+0Star
* RISC-V: Allow both Zmmul and MPalmer Dabbelt2022-07-271-5/+0Star
* target/riscv: Update default priority table for local interruptsAnup Patel2022-07-032-70/+66Star
* target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel2022-07-032-168/+6Star
* target/riscv: Set minumum priv spec version for mcountinhibitAnup Patel2022-07-031-1/+1
* target/riscv: Don't force update priv spec version to latestAnup Patel2022-07-031-4/+8
* target/riscv: Ibex: Support priv version 1.11Alistair Francis2022-07-031-1/+1
* target/riscv: Fixup MSECCFG minimum priv checkAlistair Francis2022-07-031-1/+1
* target/riscv: Support mcycle/minstret write operationAtish Patra2022-07-036-53/+213
* target/riscv: Add support for hpmcounters/hpmeventsAtish Patra2022-07-033-152/+331
* target/riscv: Implement mcountinhibit CSRAtish Patra2022-07-034-0/+32
* target/riscv: pmu: Make number of counters configurableAtish Patra2022-07-033-36/+63
* target/riscv: pmu: Rename the counters extension to pmuAtish Patra2022-07-033-5/+5
* target/riscv: Implement PMU CSR predicate function for S-modeAtish Patra2022-07-031-0/+51
* target/riscv: Fix PMU CSR predicate functionAtish Patra2022-07-031-4/+7
* target/riscv/pmp: guard against PMP ranges with a negative sizeNicolas Pitre2022-07-031-0/+3
* target/riscv: Minimize the calls to decode_save_opcRichard Henderson2022-07-034-9/+17
* target/riscv: Remove generate_exception_mtvalRichard Henderson2022-07-031-9/+2Star
* target/riscv: Set env->bins in gen_exception_illegalRichard Henderson2022-07-031-0/+2
* target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo2022-07-031-6/+2Star
* semihosting: Split out common-semi-target.hRichard Henderson2022-06-281-0/+50
* semihosting: Return void from do_common_semihostingRichard Henderson2022-06-281-1/+1
* target/riscv: trans_rvv: Avoid assert for RV32 and e64Alistair Francis2022-06-101-2/+10
* target/riscv: Don't expose the CPU properties on names CPUsAlistair Francis2022-06-101-11/+46
* target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnosti...eopXD2022-06-101-0/+2
* target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD2022-06-102-2/+45
* target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD2022-06-102-0/+36
* target/riscv: rvv: Add tail agnostic for vector reduction instructionseopXD2022-06-101-0/+20
* target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD2022-06-102-196/+261
* target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instruct...eopXD2022-06-101-106/+114
* target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD2022-06-102-4/+28
* target/riscv: rvv: Add tail agnostic for vector integer comparison instructionseopXD2022-06-101-0/+18
* target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD2022-06-102-1/+13
* target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructionseopXD2022-06-103-142/+190
* target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD2022-06-103-0/+68
* target/riscv: rvv: Add tail agnostic for vv instructionseopXD2022-06-106-132/+178
* target/riscv: rvv: Early exit when vstart >= vleopXD2022-06-101-0/+27
* target/riscv: rvv: Rename ambiguous eszeopXD2022-06-101-38/+38
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