summaryrefslogtreecommitdiffstats
path: root/target/riscv/cpu.c
Commit message (Expand)AuthorAgeFilesLines
* Various spelling fixesMichael Tokarev2021-03-091-1/+1
* target-riscv: support QMP dump-guest-memoryYifei Jiang2021-03-041-0/+2
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-7/+16
* cpu: move do_unaligned_access to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost2021-02-051-1/+1
* target/riscv: remove CONFIG_TCG, as it is always TCGClaudio Fontana2021-02-051-2/+1Star
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng2021-01-161-0/+12
* gdb: riscv: Add target descriptionSylvain Pelissier2021-01-161-0/+13
* tcg: Make tb arg to synchronize_from_tb constRichard Henderson2021-01-071-1/+2
* target/riscv: cpu: Set XLEN independently from targetAlistair Francis2020-12-181-9/+16
* target/riscv: cpu: Remove compile time XLEN checksAlistair Francis2020-12-181-9/+10
* target/riscv: Specify the XLEN for CPUsAlistair Francis2020-12-181-10/+23
* target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis2020-12-181-0/+9
* target/riscv: Add basic vmstate description of CPUYifei Jiang2020-11-031-7/+1Star
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-031-3/+5
* target/riscv: Set instance_align on RISCVCPU TypeInfoRichard Henderson2020-09-181-0/+1
* target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-101-5/+2Star
* target/riscv: cpu: Add a new 'resetvec' propertyBin Meng2020-09-101-0/+1
* target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang2020-09-101-0/+11
* target/riscv: configure and turn on vector extension from command lineLIU Zhiwei2020-07-021-0/+43
* target/riscv: implementation-defined constant parametersLIU Zhiwei2020-07-021-0/+7
* hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2020-06-191-8/+8
* target/riscv: Rename IBEX CPU init routineBin Meng2020-06-191-2/+2
* riscv: Keep the CPU init routine names consistentBin Meng2020-06-191-4/+4
* riscv: Generalize CPU init routine for the imacu CPUBin Meng2020-06-191-21/+10Star
* riscv: Generalize CPU init routine for the gcsu CPUBin Meng2020-06-191-14/+6Star
* riscv: Generalize CPU init routine for the base CPUBin Meng2020-06-191-13/+5Star
* Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...Peter Maydell2020-06-081-2/+4
|\
| * target/riscv/cpu: Restrict CPU migration to system-modePhilippe Mathieu-Daudé2020-06-051-2/+4
* | target/riscv: Add the lowRISC Ibex CPUAlistair Francis2020-06-031-0/+10
* | target/riscv: Don't set PMP feature in the cpu initAlistair Francis2020-06-031-5/+0Star
* | target/riscv: Disable the MMU correctlyAlistair Francis2020-06-031-2/+3
* | target/riscv: Don't overwrite the reset vectorAlistair Francis2020-06-031-1/+2
* | target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis2020-06-031-2/+0Star
* | target/riscv: Remove the deprecated CPUsAlistair Francis2020-06-031-28/+0Star
|/
* target/riscv: Add a sifive-e34 cpu typeCorey Wharton2020-04-291-0/+10
* cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-181-3/+4
* RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt2020-03-051-2/+2
* target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2020-02-271-0/+5
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-271-0/+3
* target/riscv: Dump Hypervisor registers if enabledAlistair Francis2020-02-271-0/+33
* target/riscv: Rename the H irqs to VS irqsAlistair Francis2020-02-271-3/+3
* target/riscv: Add support for the new execption numbersAlistair Francis2020-02-271-0/+8
* target/riscv: Convert MIP CSR to target_ulongAlistair Francis2020-02-271-1/+1
* qdev: set properties with device_class_set_props()Marc-André Lureau2020-01-241-1/+1
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 14:08:05 +0100