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path: root/target/riscv/cpu.c
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* target/riscv: rvb: add b-ext version cpu optionFrank Chang2021-06-081-0/+23
* target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2021-06-081-0/+4
* target/riscv: Dump CSR mscratch/sscratch/satpChangbin Du2021-06-081-2/+5
* target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2021-06-081-2/+2
* hw/core: Constify TCGCPUOpsRichard Henderson2021-05-271-1/+1
* cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Move CPUClass::write_elf* to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-2/+2
* cpu: Move CPUClass::vmsd to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé2021-05-271-0/+8
* cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé2021-05-271-2/+1Star
* target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis2021-05-111-1/+5
* target/riscv: fix a typo with interrupt namesEmmanuel Blot2021-05-111-1/+1
* target/riscv: Add ePMP support for the Ibex CPUAlistair Francis2021-05-111-0/+1
* target/riscv: Add a config option for ePMPHou Weiying2021-05-111-0/+10
* target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis2021-05-111-1/+1
* target/riscv: Add Shakti C class CPUVijai Kumar K2021-05-111-0/+1
* target/riscv: Align the data type of reset vector addressDylan Jhong2021-05-111-1/+1
* target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-111-1/+1
* target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer2021-03-231-0/+1
* Various spelling fixesMichael Tokarev2021-03-091-1/+1
* target-riscv: support QMP dump-guest-memoryYifei Jiang2021-03-041-0/+2
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-7/+16
* cpu: move do_unaligned_access to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost2021-02-051-1/+1
* target/riscv: remove CONFIG_TCG, as it is always TCGClaudio Fontana2021-02-051-2/+1Star
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng2021-01-161-0/+12
* gdb: riscv: Add target descriptionSylvain Pelissier2021-01-161-0/+13
* tcg: Make tb arg to synchronize_from_tb constRichard Henderson2021-01-071-1/+2
* target/riscv: cpu: Set XLEN independently from targetAlistair Francis2020-12-181-9/+16
* target/riscv: cpu: Remove compile time XLEN checksAlistair Francis2020-12-181-9/+10
* target/riscv: Specify the XLEN for CPUsAlistair Francis2020-12-181-10/+23
* target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis2020-12-181-0/+9
* target/riscv: Add basic vmstate description of CPUYifei Jiang2020-11-031-7/+1Star
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-031-3/+5
* target/riscv: Set instance_align on RISCVCPU TypeInfoRichard Henderson2020-09-181-0/+1
* target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-101-5/+2Star
* target/riscv: cpu: Add a new 'resetvec' propertyBin Meng2020-09-101-0/+1
* target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang2020-09-101-0/+11
* target/riscv: configure and turn on vector extension from command lineLIU Zhiwei2020-07-021-0/+43
* target/riscv: implementation-defined constant parametersLIU Zhiwei2020-07-021-0/+7
* hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2020-06-191-8/+8
* target/riscv: Rename IBEX CPU init routineBin Meng2020-06-191-2/+2
* riscv: Keep the CPU init routine names consistentBin Meng2020-06-191-4/+4
* riscv: Generalize CPU init routine for the imacu CPUBin Meng2020-06-191-21/+10Star
* riscv: Generalize CPU init routine for the gcsu CPUBin Meng2020-06-191-14/+6Star
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