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path: root/target/riscv/cpu_helper.c
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* target/riscv: Split out the vill from vtypeLIU Zhiwei2022-01-211-2/+1Star
* target/riscv: Split pm_enabled into mask and baseLIU Zhiwei2022-01-211-18/+6Star
* target/riscv: Create current pm fields in envLIU Zhiwei2022-01-211-0/+43
* target/riscv: Ignore the pc bits above XLENLIU Zhiwei2022-01-211-1/+1
* target/riscv: Create xl field in envLIU Zhiwei2022-01-211-32/+2Star
* target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang2022-01-211-1/+1
* target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang2022-01-211-1/+4
* target/riscv: Implement the stval/mtval illegal instructionAlistair Francis2022-01-081-0/+3
* target/riscv: Fixup setting GVAAlistair Francis2022-01-081-15/+6Star
* target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang2021-12-201-3/+13
* target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang2021-12-201-0/+3
* target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei2021-12-201-1/+19
* target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-021-20/+1Star
* target/riscv: remove force HS exceptionJose Martins2021-10-291-25/+1Star
* target/riscv: fix VS interrupts forwarding to HSJose Martins2021-10-291-20/+8Star
* target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev2021-10-281-0/+18
* target/riscv: Compute mstatus.sd on demandRichard Henderson2021-10-221-2/+1Star
* target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson2021-10-211-0/+33
* target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-211-6/+6
* target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson2021-10-211-0/+46
* target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang2021-09-211-1/+2
* target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-141-5/+0Star
* target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis2021-05-111-8/+24
* target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis2021-05-111-9/+15
* target/riscv: fix exception index on instruction access faultEmmanuel Blot2021-05-111-1/+3
* riscv: don't look at SUM when accessing memory from a debugger contextJade Fink2021-05-111-8/+12
* target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis2021-05-111-2/+2
* target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-111-6/+6
* target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer2021-03-231-13/+8Star
* target/riscv: Use background registers also for MSTATUS_MPVGeorg Kotheimer2021-03-231-1/+1
* target/riscv: Adjust privilege level for HLV(X)/HSV instructionsGeorg Kotheimer2021-03-231-11/+14
* target/riscv: add log of PMP permission checkingJim Shu2021-03-231-0/+12
* target/riscv: propagate PMP permission to TLB pageJim Shu2021-03-231-21/+63
* semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé2021-03-101-1/+1
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-051-1/+1
* riscv: Add semihosting supportKeith Packard2021-01-181-0/+10
* target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis2020-12-181-5/+7
* target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang2020-12-181-1/+2
* target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis2020-11-101-36/+24Star
* target/riscv: Add a virtualised MMU ModeAlistair Francis2020-11-101-1/+1
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-031-28/+7Star
* target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang2020-10-221-9/+27
* target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interruptGeorg Kotheimer2020-10-221-1/+3
* target/riscv: Fix update of hstatus.SPVPGeorg Kotheimer2020-10-221-1/+1
* riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis2020-10-221-1/+7
* qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi2020-09-231-1/+1
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+3
* target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang2020-09-101-2/+2
* target/riscv: Update the Hypervisor trap return/entryAlistair Francis2020-08-251-10/+6Star
* target/riscv: Fix the interrupt cause codeAlistair Francis2020-08-251-2/+3
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