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path: root/target/riscv/cpu_helper.c
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* semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé2021-03-101-1/+1
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-051-1/+1
* riscv: Add semihosting supportKeith Packard2021-01-181-0/+10
* target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis2020-12-181-5/+7
* target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang2020-12-181-1/+2
* target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis2020-11-101-36/+24Star
* target/riscv: Add a virtualised MMU ModeAlistair Francis2020-11-101-1/+1
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-031-28/+7Star
* target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang2020-10-221-9/+27
* target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interruptGeorg Kotheimer2020-10-221-1/+3
* target/riscv: Fix update of hstatus.SPVPGeorg Kotheimer2020-10-221-1/+1
* riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis2020-10-221-1/+7
* qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi2020-09-231-1/+1
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+3
* target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang2020-09-101-2/+2
* target/riscv: Update the Hypervisor trap return/entryAlistair Francis2020-08-251-10/+6Star
* target/riscv: Fix the interrupt cause codeAlistair Francis2020-08-251-2/+3
* target/riscv: Convert MSTATUS MTL to GVAAlistair Francis2020-08-251-4/+20
* target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructionsAlistair Francis2020-08-251-35/+25Star
* target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis2020-08-251-0/+18
* target/riscv: Change the TLB page size depends on PMP entries.Zong Li2020-08-221-2/+8
* target/riscv: Fix the translation of physical addressZong Li2020-08-221-2/+3
* target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis2020-06-191-2/+7
* target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis2020-06-191-1/+1
* target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis2020-06-031-53/+29Star
* riscv: Fix Stage2 SV32 page table walkAnup Patel2020-04-291-6/+1Star
* riscv: AND stage-1 and stage-2 protection flagsAlistair Francis2020-04-291-3/+5
* riscv: Don't use stage-2 PTE lookup protection flagsAlistair Francis2020-04-291-1/+2
* target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal2020-03-171-1/+8
* target/riscv: Emulate TIME CSRs for privileged modeAnup Patel2020-02-271-0/+5
* target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis2020-02-271-2/+2
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-271-0/+17
* target/riscv: Set htval and mtval2 on execptionsAlistair Francis2020-02-271-0/+10
* target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis2020-02-271-6/+18
* target/riscv: Implement second stage MMUAlistair Francis2020-02-271-19/+174
* target/riscv: Allow specifying MMU stageAlistair Francis2020-02-271-9/+28
* target/riscv: Disable guest FP support based on virtual statusAlistair Francis2020-02-271-0/+3
* target/riscv: Add hypvervisor trap supportAlistair Francis2020-02-271-10/+59
* target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis2020-02-271-0/+5
* target/riscv: Add support for virtual interrupt settingAlistair Francis2020-02-271-5/+28
* target/riscv: Add virtual register swapping functionAlistair Francis2020-02-271-0/+61
* target/riscv: Add the force HS exception modeAlistair Francis2020-02-271-0/+18
* target/riscv: Add the virtulisation modeAlistair Francis2020-02-271-0/+18
* target/riscv: Add support for the new execption numbersAlistair Francis2020-02-271-2/+5
* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
* target/riscv: Remove atomic accesses to MIP CSRAlistair Francis2019-11-141-30/+18Star
* linux-user/riscv: Propagate fault addressGiuseppe Musacchio2019-10-281-1/+4
* RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt2019-10-281-4/+7
* RISC-V: Handle bus errors in the page table walkerPalmer Dabbelt2019-10-281-3/+9
* riscv: rv32: Root page table address can be larger than 32-bitBin Meng2019-09-171-5/+5
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