summaryrefslogtreecommitdiffstats
path: root/target/riscv/insn_trans
Commit message (Expand)AuthorAgeFilesLines
* target/riscv: rvb: add/shift with prefix zero-extendKito Cheng2021-06-081-0/+26
* target/riscv: rvb: address calculationKito Cheng2021-06-081-0/+24
* target/riscv: rvb: generalized or-combineFrank Chang2021-06-081-0/+26
* target/riscv: rvb: generalized reverseFrank Chang2021-06-081-0/+31
* target/riscv: rvb: rotate (left/right)Kito Cheng2021-06-081-0/+39
* target/riscv: rvb: shift onesKito Cheng2021-06-081-0/+52
* target/riscv: rvb: single-bit instructionsFrank Chang2021-06-081-0/+97
* target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang2021-06-081-50/+4Star
* target/riscv: rvb: sign-extend instructionsKito Cheng2021-06-081-0/+12
* target/riscv: rvb: min/max instructionsKito Cheng2021-06-081-0/+24
* target/riscv: rvb: pack two words into one registerKito Cheng2021-06-081-0/+32
* target/riscv: rvb: logic-with-negateKito Cheng2021-06-081-0/+18
* target/riscv: rvb: count bits setFrank Chang2021-06-081-0/+13
* target/riscv: rvb: count leading/trailing zerosKito Cheng2021-06-081-0/+44
* target/riscv: Pass the same value to oprsz and maxsz.LIU Zhiwei2021-06-081-39/+50
* target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis2021-05-111-0/+6
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-117-35/+77
* riscv: Add semihosting supportKeith Packard2021-01-181-1/+36
* target/riscv: Split the Hypervisor execute load helpersAlistair Francis2020-11-101-14/+6Star
* target/riscv: Remove the hyp load and store functionsAlistair Francis2020-11-101-78/+45Star
* target/riscv: Support the Virtual Instruction faultAlistair Francis2020-08-251-1/+1
* target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis2020-08-251-0/+340
* target/riscv: check before allocating TCG tempsLIU Zhiwei2020-08-222-8/+8
* target/riscv: Clean up fmv.w.xLIU Zhiwei2020-08-221-5/+1Star
* target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson2020-08-221-16/+55
* target/riscv: Generate nanboxed results from trans_rvf.inc.cRichard Henderson2020-08-221-0/+4
* target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson2020-08-221-15/+1Star
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-218-0/+0
* target/riscv: fix vector index load/store constraintsLIU Zhiwei2020-07-221-1/+9
* target/riscv: Quiet Coverity complains about vamo*LIU Zhiwei2020-07-221-0/+1
* target/riscv: fix return value of do_opivx_widen()Frank Chang2020-07-141-1/+1
* target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()Frank Chang2020-07-141-1/+1
* target/riscv: fix rsub gvec tcg_assert_listed_vecop assertionFrank Chang2020-07-141-0/+5
* target/riscv: vector compress instructionLIU Zhiwei2020-07-021-0/+32
* target/riscv: vector register gather instructionLIU Zhiwei2020-07-021-0/+78
* target/riscv: vector slide instructionsLIU Zhiwei2020-07-021-0/+18
* target/riscv: floating-point scalar move instructionsLIU Zhiwei2020-07-021-0/+49
* target/riscv: integer scalar move instructionLIU Zhiwei2020-07-021-0/+60
* target/riscv: integer extract instructionLIU Zhiwei2020-07-021-0/+116
* target/riscv: vector element index instructionLIU Zhiwei2020-07-021-0/+25
* target/riscv: vector iota instructionLIU Zhiwei2020-07-021-0/+27
* target/riscv: set-X-first mask bitLIU Zhiwei2020-07-021-0/+28
* target/riscv: vmfirst find-first-set mask bitLIU Zhiwei2020-07-021-0/+32
* target/riscv: vector mask population count vmpopcLIU Zhiwei2020-07-021-0/+32
* target/riscv: vector mask-register logical instructionsLIU Zhiwei2020-07-021-0/+35
* target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei2020-07-021-0/+3
* target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei2020-07-021-0/+5
* target/riscv: vector wideing integer reduction instructionsLIU Zhiwei2020-07-021-0/+4
* target/riscv: vector single-width integer reduction instructionsLIU Zhiwei2020-07-021-0/+18
* target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei2020-07-021-0/+48
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 02:55:57 +0100