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* target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2021-09-012-61/+26Star
* target/riscv: Tidy trans_rvh.c.incRichard Henderson2021-09-012-210/+57Star
* target/riscv: Use {get,dest}_gpr for RVDRichard Henderson2021-09-011-65/+60Star
* target/riscv: Use {get,dest}_gpr for RVFRichard Henderson2021-09-011-76/+70Star
* target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson2021-09-011-13/+6Star
* target/riscv: Use {get,dest}_gpr for RVARichard Henderson2021-09-011-28/+19Star
* target/riscv: Reorg csr instructionsRichard Henderson2021-09-013-66/+132
* target/riscv: Fix hgeie, hgeipRichard Henderson2021-09-011-18/+8Star
* target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson2021-09-011-8/+15
* target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson2021-09-011-18/+20
* target/riscv: Use get_gpr in branchesRichard Henderson2021-09-011-15/+10Star
* target/riscv: Use extracts for sraiw and srliwRichard Henderson2021-09-011-2/+12
* target/riscv: Use DisasExtend in shift operationsRichard Henderson2021-09-013-202/+125Star
* target/riscv: Add DisasExtend to gen_unaryRichard Henderson2021-09-012-23/+15Star
* target/riscv: Move gen_* helpers for RVBRichard Henderson2021-09-012-233/+234
* target/riscv: Move gen_* helpers for RVMRichard Henderson2021-09-012-127/+127
* target/riscv: Use gen_arith for mulh and mulhuRichard Henderson2021-09-011-22/+18Star
* target/riscv: Remove gen_arith_div*Richard Henderson2021-09-012-50/+8Star
* target/riscv: Add DisasExtend to gen_arith*Richard Henderson2021-09-014-90/+64Star
* target/riscv: Introduce DisasExtend and new helpersRichard Henderson2021-09-011-16/+81
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-019-144/+144
* target/riscv: Clean up division helpersRichard Henderson2021-09-011-83/+91
* target/riscv: Use tcg_constant_*Richard Henderson2021-09-013-70/+34Star
* target/riscv: Add User CSRs read-only checkLIU Zhiwei2021-09-011-3/+5
* target/riscv: Don't wrongly override isa versionLIU Zhiwei2021-09-011-6/+8
* target/riscv: Correct a comment in riscv_csrrw()Bin Meng2021-09-011-1/+1
* accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-17/+0Star
* target/riscv: hardwire bits in hideleg and hedelegJose Martins2021-07-151-23/+31
* target/riscv: csr: Remove redundant check in fp csr read/write routinesBin Meng2021-07-151-24/+0Star
* target/riscv: pmp: Fix some typosBin Meng2021-07-151-5/+5
* Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...Peter Maydell2021-07-121-19/+1Star
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| * target/riscv: Use translator_use_goto_tbRichard Henderson2021-07-091-19/+1Star
* | meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé2021-07-091-0/+5
|/
* target/riscv: gdbstub: Fix dynamic CSR XML generationBin Meng2021-06-241-1/+1
* target/riscv: Use target_ulong for the DisasContext misaAlistair Francis2021-06-241-1/+1
* target/riscv: rvb: add b-ext version cpu optionFrank Chang2021-06-082-0/+26
* target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2021-06-082-0/+5
* target/riscv: rvb: add/shift with prefix zero-extendKito Cheng2021-06-083-0/+35
* target/riscv: rvb: address calculationKito Cheng2021-06-083-0/+62
* target/riscv: rvb: generalized or-combineFrank Chang2021-06-085-0/+64
* target/riscv: rvb: generalized reverseFrank Chang2021-06-086-0/+132
* target/riscv: rvb: rotate (left/right)Kito Cheng2021-06-083-0/+81
* target/riscv: rvb: shift onesKito Cheng2021-06-083-0/+74
* target/riscv: rvb: single-bit instructionsFrank Chang2021-06-083-0/+175
* target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang2021-06-082-50/+43Star
* target/riscv: rvb: sign-extend instructionsKito Cheng2021-06-082-0/+15
* target/riscv: rvb: min/max instructionsKito Cheng2021-06-082-0/+28
* target/riscv: rvb: pack two words into one registerKito Cheng2021-06-083-0/+78
* target/riscv: rvb: logic-with-negateKito Cheng2021-06-082-0/+21
* target/riscv: rvb: count bits setFrank Chang2021-06-083-0/+21
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