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* riscv: Separate FPU register size from core register size in gdbstub [v2]Keith Packard2020-02-101-9/+11
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2020-01-271-3/+2Star
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| * qdev: set properties with device_class_set_props()Marc-André Lureau2020-01-241-1/+1
| * cpu: Use cpu_class_set_parent_reset()Greg Kurz2020-01-241-2/+1Star
* | Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' i...Peter Maydell2020-01-246-11/+5Star
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| * target/riscv: update mstatus.SD when FS is set dirtyShihPo Hung2020-01-162-3/+2Star
| * target/riscv: fsd/fsw doesn't dirty FP stateShihPo Hung2020-01-162-2/+0Star
| * target/riscv: Fix tb->flags FS statusShihPo Hung2020-01-161-4/+1Star
| * riscv: Set xPIE to 1 after xRETYiting Wang2020-01-161-2/+2
* | tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-162-2/+2
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* target/riscv: Remove atomic accesses to MIP CSRAlistair Francis2019-11-144-43/+21Star
* remove unnecessary ifdef TARGET_RISCV64hiroyuki.obinata2019-11-141-3/+1Star
* Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-plugins-281019-4'...Peter Maydell2019-10-301-1/+1
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| * target/riscv: fetch code with translator_ldEmilio G. Cota2019-10-281-1/+1
* | target/riscv: PMP violation due to wrong size parameterDayeol Lee2019-10-281-1/+12
* | target/riscv: Make the priv register writable by GDBJonathan Behrens2019-10-281-0/+9
* | target/riscv: Expose "priv" register for GDB for readsJonathan Behrens2019-10-281-0/+23
* | target/riscv: Tell gdbstub the correct number of CSRsJonathan Behrens2019-10-281-2/+2
* | linux-user/riscv: Propagate fault addressGiuseppe Musacchio2019-10-281-1/+4
* | RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt2019-10-283-7/+13
* | RISC-V: Handle bus errors in the page table walkerPalmer Dabbelt2019-10-281-3/+9
* | riscv: Skip checking CSR privilege level in debugger modeBin Meng2019-10-281-1/+4
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* gdbstub: riscv: fix the fflags registersKONRAD Frederic2019-09-171-2/+4
* target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis2019-09-171-1/+1
* target/riscv: Fix mstatus dirty maskAlistair Francis2019-09-171-1/+1
* target/riscv: Use both register name and ABI nameAtish Patra2019-09-171-8/+11
* riscv: hmp: Add a command to show virtual memory mappingsBin Meng2019-09-172-0/+233
* riscv: rv32: Root page table address can be larger than 32-bitBin Meng2019-09-171-5/+5
* target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis2019-09-171-17/+18
* target/riscv: Create function to test if FP is enabledAlistair Francis2019-09-173-10/+26
* target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace eventsPhilippe Mathieu-Daudé2019-09-172-21/+16Star
* target/riscv/pmp: Restrict priviledged PMP to system-mode emulationPhilippe Mathieu-Daudé2019-09-172-5/+2Star
* tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2019-09-032-6/+6
* Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' in...Peter Maydell2019-08-221-1/+1
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| * hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster2019-08-211-1/+1
* | icount: remove unnecessary gen_io_end callsPavel Dovgalyuk2019-08-201-1/+0Star
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* Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20190819' into stagingPeter Maydell2019-08-191-18/+1Star
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| * target/riscv: Remove redundant declaration pragmasRichard Henderson2019-08-191-18/+1Star
* | target/riscv: rationalise softfloat includesAlex Bennée2019-08-193-1/+3
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* RISC-V: Clear load reservations on context switch and SCJoel Sing2019-06-263-1/+18
* RISC-V: Add support for the Zicsr extensionPalmer Dabbelt2019-06-263-0/+8
* RISC-V: Add support for the Zifencei extensionPalmer Dabbelt2019-06-264-0/+9
* target/riscv: Add support for disabling/enabling CountersAlistair Francis2019-06-253-5/+14
* target/riscv: Remove user version informationAlistair Francis2019-06-252-25/+9Star
* target/riscv: Require either I or E base extensionAlistair Francis2019-06-251-0/+6
* target/riscv: Set privledge spec 1.11.0 as defaultAlistair Francis2019-06-251-3/+5
* target/riscv: Add the mcountinhibit CSRAlistair Francis2019-06-252-2/+16
* target/riscv: Add the privledge spec version 1.11.0Alistair Francis2019-06-242-1/+2
* target/riscv: Restructure deprecatd CPUsAlistair Francis2019-06-242-14/+17
* RISC-V: Fix a PMP check with the correct access sizeHesham Almatary2019-06-241-2/+1Star
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