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* Merge tag 'pull-target-arm-20220922' of ↵Stefan Hajnoczi2022-09-266-282/+241Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic * Fix alignment for Neon VLD4.32 * Refactoring of page-table-walk code * hw/acpi: Add ospm_status hook implementation for acpi-ged * hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level * chardev/baum: avoid variable-length arrays * io/channel-websock: avoid variable-length arrays * hw/net/e1000e_core: Use definition to avoid dynamic stack allocation * hw/ppc/pnv: Avoid dynamic stack allocation * hw/intc/xics: Avoid dynamic stack allocation * hw/i386/multiboot: Avoid dynamic stack allocation * hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation * ui/curses: Avoid dynamic stack allocation * tests/unit/test-vmstate: Avoid dynamic stack allocation * configure: fix various shellcheck-spotted issues and nits # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmMsjocZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3s0vEACuUs7nGGX5vd96EPN+sO5s # HstP16G6/Xnlw2z0BaXi0MMWapQRhSQJ+MIeDJmqIyZKQ3geJGP7pbFTxI3zreYM # UTKjdI/wWRYMKPYfxlIBZ8TPugj4a4paFJlyqmpHXtkwiWRv6rF70HQ9Yku5id93 # FN9js/dyF74S2AaDppBuTWp31cM1k6kBTg/v5tXSxE8kDUKkO+HZ1VujOqIG/4nJ # 6urNJ7jlHSiFdXya2QiR+CAkyXyy551rLETeO8VJg9tOO7Ys7Olj7lqv6kHJY/X1 # 01RbN5A5WXhqCvTLM3UYTvFHmbZtS/C5iUhHRtlZkOoeSv2jS6IRDB8BrBtIbOwF # XKpaYf1jyFLFwX++hpvySD9Vbcu8KgKId8iKTuDcxjQlEjL3fTbt1ulKo4y+rJ8O # 6G1k4yZc8/nAvttNoKCn7/Jr1dC+HsANa+1s1L+6w+f1gARV0VXs4gqsveNnbe1+ # WzzaHvHt+hCaiWkSZlyisyw3fbEXMrEyKewi+SZu3c8PvJ6DHa+rYjkhem7muBVF # iR48FRTjFiS+o402KMwXfMdiGjXyZFi09yn5diowlVjkNAaZVZfgu/wUMD5QBhbh # fNDSw7LpXGUHML/O98MiXznkgGvTEQNxZdp2qIQrTiinUgmV4ZRLR23ZpEibdJPX # kiOkr46SbWvksCXnRlTf8w== # =hec8 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 22 Sep 2022 12:34:15 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20220922' of https://git.linaro.org/people/pmaydell/qemu-arm: (39 commits) configure: Avoid use of 'local' as it is non-POSIX configure: Check mkdir result directly, not via $? configure: Remove use of backtick `...` syntax configure: Add './' on front of glob of */config-devices.mak.d configure: Add missing quoting for some easy cases configure: Remove unused meson_args variable configure: Remove unused python_version variable tests/unit/test-vmstate: Avoid dynamic stack allocation ui/curses: Avoid dynamic stack allocation hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation hw/i386/multiboot: Avoid dynamic stack allocation hw/intc/xics: Avoid dynamic stack allocation hw/ppc/pnv: Avoid dynamic stack allocation hw/net/e1000e_core: Use definition to avoid dynamic stack allocation io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1 chardev/baum: Avoid dynamic stack allocation chardev/baum: Use definitions to avoid dynamic stack allocation chardev/baum: Replace magic values by X_MAX / Y_MAX definitions hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level hw/acpi: Add ospm_status hook implementation for acpi-ged ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * target/arm: Add is_secure parameter to get_phys_addr_pmsav5Richard Henderson2022-09-221-2/+2
| | | | | | | | | | | | | | | | | | | | Remove the use of regime_is_secure from get_phys_addr_pmsav5. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-21-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add secure parameter to get_phys_addr_pmsav7Richard Henderson2022-09-221-3/+2Star
| | | | | | | | | | | | | | | | | | | | | | Remove the use of regime_is_secure from get_phys_addr_pmsav7, using the new parameter instead. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-19-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add is_secure parameter to pmsav7_use_background_regionRichard Henderson2022-09-221-5/+5
| | | | | | | | | | | | | | | | | | | | | | Remove the use of regime_is_secure from pmsav7_use_background_region, using the new parameter instead. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-17-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add secure parameter to get_phys_addr_pmsav8Richard Henderson2022-09-221-3/+2Star
| | | | | | | | | | | | | | | | | | | | | | Remove the use of regime_is_secure from get_phys_addr_pmsav8. Since we already had a local variable named secure, use that. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-16-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add is_secure parameter to get_phys_addr_v6Richard Henderson2022-09-221-6/+5Star
| | | | | | | | | | | | | | | | | | | | | | Remove the use of regime_is_secure from get_phys_addr_v6, passing the new parameter to the lookup instead. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-15-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add is_secure parameter to get_phys_addr_v5Richard Henderson2022-09-221-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove the use of regime_is_secure from get_phys_addr_v5, passing the new parameter to the lookup instead. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMM: Folded in definition of local is_secure in get_phys_addr(), since I dropped the earlier patch that would have provided it] Message-id: 20220822152741.1617527-14-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add secure parameter to pmsav8_mpu_lookupRichard Henderson2022-09-223-7/+6Star
| | | | | | | | | | | | | | | | | | | | | | Remove the use of regime_is_secure from pmsav8_mpu_lookup, passing the new parameter to the lookup instead. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-13-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add is_secure parameter to v8m_security_lookupRichard Henderson2022-09-223-8/+12
| | | | | | | | | | | | | | | | | | | | | | Remove the use of regime_is_secure from v8m_security_lookup, passing the new parameter to the lookup instead. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-12-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Remove is_subpage argument to pmsav8_mpu_lookupRichard Henderson2022-09-223-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | This can be made redundant with result->page_size, by moving the basic set of page_size from get_phys_addr_pmsav8. We still need to overwrite page_size when v8m_security_lookup signals a subpage. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-11-richard.henderson@linaro.org [PMM: Update a comment that used to refer to is_subpage] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookupRichard Henderson2022-09-223-26/+21Star
| | | | | | | | | | | | | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8Richard Henderson2022-09-221-14/+14
| | | | | | | | | | | | | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7Richard Henderson2022-09-221-19/+17Star
| | | | | | | | | | | | | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5Richard Henderson2022-09-221-12/+12
| | | | | | | | | | | | | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use GetPhysAddrResult in get_phys_addr_v5Richard Henderson2022-09-221-14/+11Star
| | | | | | | | | | | | | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use GetPhysAddrResult in get_phys_addr_v6Richard Henderson2022-09-221-16/+14Star
| | | | | | | | | | | | | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use GetPhysAddrResult in get_phys_addr_lpaeRichard Henderson2022-09-221-43/+26Star
| | | | | | | | | | | | | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Create GetPhysAddrResultRichard Henderson2022-09-225-125/+109Star
| | | | | | | | | | | | | | | | | | | | Combine 5 output pointer arguments from get_phys_addr into a single struct. Adjust all callers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220822152741.1617527-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Fix alignment for VLD4.32Clément Chigot2022-09-221-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When requested, the alignment for VLD4.32 is 8 and not 16. See ARM documentation about VLD4 encoding: ebytes = 1 << UInt(size); if size == '10' then alignment = if a == '0' then 1 else 8; else alignment = if a == '0' then 1 else 4*ebytes; Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220914105058.2787404-1-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge tag 'pull-hex-20220919' of https://github.com/quic/qemu into stagingStefan Hajnoczi2022-09-221-23/+0Star
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hexagon update remove unused encodings add fmin/fmax tests for signed zero # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmMou7IACgkQewJE+xLe # RCIYbQgAgjFujecgbbCJfBPVMmpTXNOgk+Jt3w+jfg7/WJRZuhxAU3xB2qpismUH # 5MntMlFHAGOjlPXfg6U5AZFSw3RhlanH/RChHpVKuL6peOXFImIfEqdyVXHXfCuu # FlpQFGwJ3Rs50UJhd7lVdlx0I7lup4E4X77hFvFcZQP6aNrt6Ic1Zq5eXhEq9k2A # NnXol1R416JRT/senujYVvcTpgYVHlQCS+4dJEzKUqvFlTdo7lnAbPdjO8MPrz7B # 0NgPUGjGZJ70Dcqvd1n8HePIU1YyKTlHJNaWyTlAmw4MECyHyAJnd64jEMNECDb5 # 0BrpHcY1HCt1Rh4QratemTfJglAJlA== # =UUyr # -----END PGP SIGNATURE----- # gpg: Signature made Mon 19 Sep 2022 14:57:54 EDT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20220919' of https://github.com/quic/qemu: Hexagon (tests/tcg/hexagon): add fmin/fmax tests for signed zero Hexagon (target/hexagon) remove unused encodings Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * Hexagon (target/hexagon) remove unused encodingsTaylor Simpson2022-09-191-23/+0Star
| | | | | | | | | | | | | | | | Remove encodings guarded by ifdef that is not defined Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220606222327.7682-4-tsimpson@quicinc.com>
* | Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k ↵Stefan Hajnoczi2022-09-215-89/+118
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging m68k pull request 20220921 - several fixes for SR - implement TAS - feature cleanup # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmMrMx0SHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748UB0P/1w5w+ogpcWVp9uBPE9m6lTT8sTricWD # oGMIEG0kgpS3xTp7pZ/WeCp38IShFBfBcz5aypvR5nS/1aclyJnzGsCqyWdBe9c4 # jJJY5r7JKP2aKcolGNilNyd20ldOiaxZGe6yFLJDWi2spFbRx3iiRJ4/2NXF5Xi8 # TlHKdlDGlNLFiFNtBXMMwqvL77qJ8LH/aE4cAr8JTOb1VszKXrFxqEqxoUucRirB # u0LbM+DP3u2xXjTGLMLlMcKf9X2BXwuWBSAXslB8xWmRlX+B6fMudBFglTgbu0Cc # bpoBBqY4s3QYPb21i89osYevJAJSdrtEzkKus3xAI08ACSffb9k9m/naVJJDSSNC # HZeKVbAd7I0Xw2xzzO5yQB+7rdfgoL1miE1rs936WKHi0WWHZpdJqzl/3G3ZPhRz # NmqczF9rRR9B9SabXx5lWlhK+Ys/W7PzY+R4gc6ose0wF4T70qmVF3EoioP1c5Y8 # 6OonMpRu6L5sW5KM3IUmkBo3KcnLezlxtebfaDyaKC9tB0qg4aM14ikL36nsLFbh # 2nGExYSyMJ6U4tqpxyQxijMMSQG20vyVIup6cUsrSD+rGmbSuWZWJwsTmaAw2W6k # 6HtDgtFk40ZB1WttYupQBa/LgjshGLl28jyLI9nNEdFYb4H1JAallEERF/tb6AUD # WEiu8vcUMYEp # =IAMt # -----END PGP SIGNATURE----- # gpg: Signature made Wed 21 Sep 2022 11:51:57 EDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k: target/m68k: always call gen_exit_tb() after writes to SR target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K target/m68k: Perform writback before modifying SR target/m68k: Fix MACSR to CCR target/m68k: Implement atomic test-and-set Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | target/m68k: always call gen_exit_tb() after writes to SRMark Cave-Ayland2022-09-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Any write to SR can change the security state so always call gen_exit_tb() when this occurs. In particular MacOS makes use of andiw/oriw in a few places to handle the switch between user and supervisor mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220917112515.83905-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68KMark Cave-Ayland2022-09-215-74/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The M68K_FEATURE_M68000 feature is misleading in that its name suggests the feature is defined just for Motorola 68000 CPUs, whilst in fact it is defined for all Motorola 680X0 CPUs. In order to avoid confusion with the other M68K_FEATURE_M680X0 constants which define the features available for specific Motorola CPU models, rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K and add comments to clarify its usage. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220917112515.83905-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | target/m68k: Perform writback before modifying SRRichard Henderson2022-09-211-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Writes to SR may change security state, which may involve a swap of %ssp with %usp as reflected in %a7. Finish the writeback of %sp@+ before swapping stack pointers. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1206 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220913142818.7802-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | target/m68k: Fix MACSR to CCRRichard Henderson2022-09-211-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, we were writing to the entire SR register, instead of only the flags portion. Second, we were not clearing C as per the documentation (X was cleared via the 0xf mask). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220913142818.7802-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | target/m68k: Implement atomic test-and-setRichard Henderson2022-09-211-10/+30
| |/ | | | | | | | | | | | | | | | | | | This is slightly more complicated than cas, because tas is allowed on data registers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220829051746.227094-1-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | Merge tag 'pull-ppc-20220920' of https://gitlab.com/danielhb/qemu into stagingStefan Hajnoczi2022-09-2112-81/+272
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ppc patch queue for 2022-09-20: This queue contains a implementation of PowerISA 3.1B hash insns, ppc TCG insns cleanups and fixes, and miscellaneus fixes in the spapr and pnv_phb models. # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCYyoWlAAKCRA82cqW3gMx # ZDYhAP0eQMeA4NS3hiw7WMcAVg0pei3ZJL9oEh1UE3+MfK7MhQEA0q8qExWnQJAA # a0hfnFH9pLjI+v0f/FbFK6QJBpu/bg8= # =qT+H # -----END PGP SIGNATURE----- # gpg: Signature made Tue 20 Sep 2022 15:37:56 EDT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20220920' of https://gitlab.com/danielhb/qemu: hw/ppc/spapr: Fix code style problems reported by checkpatch hw/pci-host: pnv_phb{3, 4}: Fix heap out-of-bound access failure hw/ppc: spapr: Use qemu_vfree() to free spapr->htab target/ppc: Clear fpstatus flags on helpers missing it target/ppc: Zero second doubleword of VSR registers for FPR insns target/ppc: Set OV32 when OV is set target/ppc: Zero second doubleword for VSX madd instructions target/ppc: Set result to QNaN for DENBCD when VXCVI occurs target/ppc: Zero second doubleword in DFP instructions target/ppc: Remove unused xer_* macros target/ppc: Remove extra space from s128 field in ppc_vsr_t target/ppc: Merge fsqrt and fsqrts helpers target/ppc: Move fsqrts to decodetree target/ppc: Move fsqrt to decodetree target/ppc: Implement hashstp and hashchkp target/ppc: Implement hashst and hashchk target/ppc: Add HASHKEYR and HASHPKEYR SPRs Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | target/ppc: Clear fpstatus flags on helpers missing itVíctor Colombo2022-09-201-11/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In ppc emulation, exception flags are not cleared at the end of an instruction. Instead, the next instruction is responsible to clear it before its emulation. However, some helpers are not doing it, causing an issue where the previously set exception flags are being used and leading to incorrect values being set in FPSCR. Fix this by clearing fp_status before doing the instruction 'real' work for the following helpers that were missing this behavior: - VSX_CVT_INT_TO_FP_VECTOR - VSX_CVT_FP_TO_FP - VSX_CVT_FP_TO_INT_VECTOR - VSX_CVT_FP_TO_INT2 - VSX_CVT_FP_TO_INT - VSX_CVT_FP_TO_FP_HP - VSX_CVT_FP_TO_FP_VECTOR - VSX_CMP - VSX_ROUND - xscvqpdp - xscvdpsp[n] Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-9-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Zero second doubleword of VSR registers for FPR insnsVíctor Colombo2022-09-201-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FPR register are mapped to the first doubleword of the VSR registers. Since PowerISA v3.1, the second doubleword of the target register must be zeroed for FP instructions. This patch does it by writting 0 to the second dw everytime the first dw is being written using set_fpr. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-8-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Set OV32 when OV is setVíctor Colombo2022-09-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to PowerISA: "OV32 is set whenever OV is implicitly set, and is set to the same value that OV is defined to be set to in 32-bit mode". This patch changes helper_update_ov_legacy to set/clear ov32 when applicable. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-7-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Zero second doubleword for VSX madd instructionsVíctor Colombo2022-09-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In 205eb5a89e we updated most VSX instructions to zero the second doubleword, as is requested by PowerISA since v3.1. However, VSX_MADD helper was left behind unchanged, while it is also affected and should be fixed as well. This patch applies the fix for MADD instructions. Fixes: 205eb5a89e ("target/ppc: Change VSX instructions behavior to fill with zeros") Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-6-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Set result to QNaN for DENBCD when VXCVI occursVíctor Colombo2022-09-201-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the ISA, for instruction DENBCD: "If an invalid BCD digit or sign code is detected in the source operand, an invalid-operation exception (VXCVI) occurs." In the Invalid Operation Exception section, there is the situation: "When Invalid Operation Exception is disabled (VE=0) and Invalid Operation occurs (...) If the operation is an (...) or format the target FPR is set to a Quiet NaN". This was not being done in QEMU. This patch sets the result to QNaN when the instruction DENBCD causes an Invalid Operation Exception. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-5-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Zero second doubleword in DFP instructionsVíctor Colombo2022-09-201-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting at PowerISA v3.1, the second doubleword of the registers used to store results in DFP instructions are supposed to be zeroed. From the ISA, chapter 7.2.1.1 Floating-Point Registers: """ Chapter 4. Floating-Point Facility provides 32 64-bit FPRs. Chapter 5. Decimal Floating-Point also employs FPRs in decimal floating-point (DFP) operations. When VSX is implemented, the 32 FPRs are mapped to doubleword 0 of VSRs 0-31. (...) All instructions that operate on an FPR are redefined to operate on doubleword element 0 of the corresponding VSR. (...) and the contents of doubleword element 1 of the VSR corresponding to the target FPR or FPR pair for these instructions are set to 0. """ Before, the result stored at doubleword 1 was said to be undefined. With that, this patch changes the DFP facility to zero doubleword 1 when using set_dfp64 and set_dfp128. This fixes the behavior for ISA 3.1 while keeping the behavior correct for previous ones. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-4-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Remove unused xer_* macrosVíctor Colombo2022-09-201-4/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The macros xer_ov, xer_ca, xer_ov32, and xer_ca32 are both unused and hiding the usage of env. Remove them. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-3-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Remove extra space from s128 field in ppc_vsr_tVíctor Colombo2022-09-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Very trivial rogue space removal. There are two spaces between Int128 and s128 in ppc_vsr_t struct, where it should be only one. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220906125523.38765-2-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Merge fsqrt and fsqrts helpersVíctor Colombo2022-09-203-26/+17Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These two helpers are almost identical, differing only by the softfloat operation it calls. Merge them into one using a macro. Also, take this opportunity to capitalize the helper name as we moved the instruction to decodetree in a previous patch. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220905123746.54659-4-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Move fsqrts to decodetreeVíctor Colombo2022-09-203-23/+2Star
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220905123746.54659-3-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Move fsqrt to decodetreeVíctor Colombo2022-09-203-13/+24
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220905123746.54659-2-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Implement hashstp and hashchkpVíctor Colombo2022-09-204-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implementation for instructions hashstp and hashchkp, the privileged versions of hashst and hashchk, which were added in Power ISA 3.1B. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Message-Id: <20220715205439.161110-4-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Implement hashst and hashchkVíctor Colombo2022-09-205-0/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implementation for instructions hashst and hashchk, which were added in Power ISA 3.1B. It was decided to implement the hash algorithm from ground up in this patch exactly as described in Power ISA. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Message-Id: <20220715205439.161110-3-victor.colombo@eldorado.org.br> [danielhb: fix block comment in excp_helper.c] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * | target/ppc: Add HASHKEYR and HASHPKEYR SPRsVíctor Colombo2022-09-202-0/+30
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Special Purpose Registers HASHKEYR and HASHPKEYR, which were introduced by the Power ISA 3.1B. They are used by the new instructions hashchk(p) and hashst(p). The ISA states that the Operating System should generate the value for these registers when creating a process, so it's its responsability to do so. We initialize it with 0 for qemu-softmmu, and set a random 64 bits value for linux-user. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Message-Id: <20220715205439.161110-2-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/i386: introduce insn_get_addrPaolo Bonzini2022-09-191-10/+26
| | | | | | | | | | | | | | | | | | The "O" operand type in the Intel SDM needs to load an 8- to 64-bit unsigned value, while insn_get is limited to 32 bits. Extract the code out of disas_insn and into a separate function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target/i386: REPZ and REPNZ are mutually exclusivePaolo Bonzini2022-09-191-0/+2
| | | | | | | | | | | | | | The later prefix wins if both are present, make it show in s->prefix too. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target/i386: fix INSERTQ implementationPaolo Bonzini2022-09-193-8/+18
| | | | | | | | | | | | | | | | | | INSERTQ is defined to not modify any bits in the lower 64 bits of the destination, other than the ones being replaced with bits from the source operand. QEMU instead is using unshifted bits from the source for those bits. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target/i386: correctly mask SSE4a bit indices in register operandsPaolo Bonzini2022-09-191-2/+2
| | | | | | | | | | | | | | | | | | | | SSE4a instructions EXTRQ and INSERTQ have two bit index operands, that can be immediates or taken from an XMM register. In both cases, the fields are 6-bit wide and the top two bits in the byte are ignored. translate.c is doing that correctly for the immediate case, but not for the XMM case, so fix it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target/i386: Raise #GP on unaligned m128 accesses when required.Paolo Bonzini2022-09-186-29/+72
|/ | | | | | | | | | | | | | | | | | | | | | Many instructions which load/store 128-bit values are supposed to raise #GP when the memory operand isn't 16-byte aligned. This includes: - Instructions explicitly requiring memory alignment (Exceptions Type 1 in the "AVX and SSE Instruction Exception Specification" section of the SDM) - Legacy SSE instructions that load/store 128-bit values (Exceptions Types 2 and 4). This change sets MO_ALIGN_16 on 128-bit memory accesses that require 16-byte alignment. It adds cpu_record_sigbus and cpu_do_unaligned_access hooks that simulate a #GP exception in qemu-user and qemu-system, respectively. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/217 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ricky Zhou <ricky@rzhou.org> Message-Id: <20220830034816.57091-2-ricky@rzhou.org> [Do not bother checking PREFIX_VEX, since AVX is not supported. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge tag 'pull-semi-20220914' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2022-09-1714-520/+182Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert m68k to semihosting/syscalls.h. Convert nios2 to semihosting/syscalls.h. Allow optional use of semihosting from userspace. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmMh1W8dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8ptggAimuNN6IiD19Huu5F # PMjzDqFPvWFOf82O16WTBM1xN0lwVH8+02PYRL3AhOIw9ZTgxezOo9/KXZpr8a8Z # gocr4Ge/J7zHzHahYuqcyOqqkur2dM4lFiK9rfDD6vdNBMbi0kQZVuaNlQK6rV6Z # 2LHEwKKh64MXJVfwGzK7OLMv4pu0wpWcuCTH2/6U4E1325SOKmEos1VzIePxY1bw # +AMNnairGEdBX1b3JlzZfrLSaOapJcgl0HZdrg6Mflm6ttTuuykGGtjkWBfcu3Nw # utNI1zmUYfD/iJbnbsCNpZSLv6LVOQ2l5S6dOWV+JJ1HukVTZu3DoyfTr8t95kwK # UuUoqA== # =W7Yh # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 Sep 2022 09:21:51 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-semi-20220914' of https://gitlab.com/rth7680/qemu: target/riscv: Honour -semihosting-config userspace=on and enable=on target/xtensa: Honour -semihosting-config userspace=on target/nios2: Honour -semihosting-config userspace=on target/mips: Honour -semihosting-config userspace=on target/m68k: Honour -semihosting-config userspace=on target/arm: Honour -semihosting-config userspace=on semihosting: Allow optional use of semihosting from userspace target/m68k: Convert semihosting errno to gdb remote errno target/m68k: Use semihosting/syscalls.h target/nios2: Convert semihosting errno to gdb remote errno target/nios2: Use semihosting/syscalls.h Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell2022-09-133-7/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The riscv target incorrectly enabled semihosting always, whether the user asked for it or not. Call semihosting_enabled() passing the correct value to the is_userspace argument, which fixes this and also handles the userspace=on argument. Because we do this at translate time, we no longer need to check the privilege level in riscv_cpu_do_interrupt(). Note that this is a behaviour change: we used to default to semihosting being enabled, and now the user must pass "-semihosting-config enable=on" if they want it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220822141230.3658237-8-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/xtensa: Honour -semihosting-config userspace=onPeter Maydell2022-09-131-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Honour the commandline -semihosting-config userspace=on option, instead of always permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(). Note that this is a behaviour change: if the user wants to do semihosting calls from userspace they must now specifically enable them on the command line. xtensa semihosting is not implemented for linux-user builds. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822141230.3658237-7-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-06 06:32:52 +0200