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* target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0()Daniel Henrique Barboza2022-01-041-1/+6
* target/ppc: Use env->pnc_cyc_cntRichard Henderson2022-01-041-98/+9Star
* target/ppc: Rewrite pmu_increment_insnsRichard Henderson2022-01-041-29/+49
* target/ppc: Cache per-pmc insn and cycle count settingsRichard Henderson2022-01-046-20/+58
* target/ppc: powerpc_excp: Stop passing excp_model aroundFabiano Rosas2022-01-041-22/+21Star
* target/ppc: powerpc_excp: Move system call vectored code togetherFabiano Rosas2022-01-041-8/+5Star
* target/ppc: powerpc_excp: Set vector earlierFabiano Rosas2022-01-041-8/+8
* target/ppc: powerpc_excp: Add excp_vectors bounds checkFabiano Rosas2022-01-041-3/+4
* target/ppc: powerpc_excp: Set alternate SRRs directlyFabiano Rosas2022-01-041-15/+8Star
* target/ppc: do not silence snan in xscvspdpnMatheus Ferst2022-01-041-4/+1Star
* ppc/ppc405: Dump specific registersCédric Le Goater2022-01-041-6/+21
* ppc/ppc405: Introduce a store helper for SPR_40x_PIDCédric Le Goater2022-01-043-1/+10
* ppc/ppc405: Restore TCR and STR write handlersCédric Le Goater2022-01-046-2/+30
* ppc/ppc405: Activate MMU logsCédric Le Goater2022-01-042-139/+122Star
* target/ppc: Print out literal exception names in logsCédric Le Goater2022-01-041-1/+74
* target/ppc: Remove static inlineCédric Le Goater2022-01-041-6/+6
* target/ppc: Check effective address validityCédric Le Goater2022-01-042-0/+6
* target/ppc: Improve logging in Radix MMUCédric Le Goater2022-01-041-3/+52
* target/hppa: Fix atomic_store_3 for STBYRichard Henderson2021-12-311-12/+15
* target/hppa: Fix deposit assert from trans_shrpw_immRichard Henderson2021-12-241-7/+12
* target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta2021-12-201-4/+4
* target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang2021-12-202-6/+13
* target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang2021-12-204-8/+8
* target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang2021-12-204-0/+67
* target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang2021-12-201-18/+18
* target/riscv: rvv-1.0: add vsetivli instructionFrank Chang2021-12-202-0/+29
* target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11Frank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang2021-12-204-0/+197
* target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang2021-12-204-0/+189
* target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang2021-12-203-0/+187
* target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang2021-12-201-0/+22
* target/riscv: rvv-1.0: implement vstart CSRFrank Chang2021-12-205-103/+199
* target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang2021-12-203-4/+4
* target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang2021-12-204-44/+97
* target/riscv: add "set round to odd" rounding mode helper functionFrank Chang2021-12-204-0/+14
* target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang2021-12-204-14/+63
* target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang2021-12-202-36/+59
* target/riscv: introduce floating-point rounding mode enumFrank Chang2021-12-203-15/+24
* target/riscv: rvv-1.0: floating-point min/max instructionsFrank Chang2021-12-201-12/+12
* target/riscv: rvv-1.0: remove integer extract instructionFrank Chang2021-12-202-24/+0Star
* target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang2021-12-204-17/+0Star
* target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang2021-12-204-243/+0Star
* target/riscv: rvv-1.0: single-width scaling shift instructionsFrank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: widening floating-point reduction instructionsFrank Chang2021-12-201-1/+8
* target/riscv: rvv-1.0: single-width floating-point reductionFrank Chang2021-12-202-9/+15
* target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang2021-12-204-50/+50
* target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang2021-12-204-45/+121
* target/riscv: rvv-1.0: slide instructionsFrank Chang2021-12-201-7/+12
* target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang2021-12-202-5/+2Star