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* tcg: Remove TCG_CT_REGRichard Henderson2020-10-081-2/+0Star
* tcg: Drop union from TCGArgConstraintRichard Henderson2020-10-081-7/+7
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-2/+2
* tcg/riscv: Remove superfluous breaksLiao Pingfang2020-07-141-2/+0Star
* tcg: Search includes in the parent source directoryPhilippe Mathieu-Daudé2020-01-161-2/+2
* tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2019-09-031-10/+10
* tcg/riscv: Fix RISC-VH host build failureAlistair Francis2019-07-091-2/+2
* cpu: Move the softmmu tlb to CPUNegativeOffsetStateRichard Henderson2019-06-101-24/+7Star
* tcg: Create struct CPUTLBRichard Henderson2019-06-101-10/+2Star
* tcg: Return bool success from tcg_out_movRichard Henderson2019-05-131-2/+3
* tcg: Restart TB generation after out-of-line ldst overflowRichard Henderson2019-04-241-4/+12
* tcg: Add INDEX_op_extract2_{i32,i64}Richard Henderson2019-04-241-0/+2
* cputlb: Remove static tlb sizingRichard Henderson2019-01-281-1/+0Star
* tcg/riscv: enable dynamic TLB sizingRichard Henderson2019-01-282-71/+55Star
* tcg: introduce dynamic TLB sizingEmilio G. Cota2019-01-281-0/+1
* tcg/riscv: Add the target init codeAlistair Francis2018-12-251-0/+31
* tcg/riscv: Add the prologue generation and register the JITAlistair Francis2018-12-251-0/+111
* tcg/riscv: Add the out op decoderAlistair Francis2018-12-251-0/+496
* tcg/riscv: Add direct load and store instructionsAlistair Francis2018-12-251-0/+158
* tcg/riscv: Add slowpath load and store instructionsAlistair Francis2018-12-251-0/+256
* tcg/riscv: Add branch and jump instructionsAlistair Francis2018-12-251-0/+145
* tcg/riscv: Add the add2 and sub2 instructionsAlistair Francis2018-12-251-0/+55
* tcg/riscv: Add the out load and store instructionsAlistair Francis2018-12-251-0/+65
* tcg/riscv: Add the extract instructionsAlistair Francis2018-12-251-0/+34
* tcg/riscv: Add the mov and movi instructionAlistair Francis2018-12-251-0/+86
* tcg/riscv: Add the relocation functionsAlistair Francis2018-12-251-0/+88
* tcg/riscv: Add the instruction emittersAlistair Francis2018-12-251-0/+48
* tcg/riscv: Add the immediate encodersAlistair Francis2018-12-251-0/+90
* tcg/riscv: Add support for the constraintsAlistair Francis2018-12-251-0/+168
* tcg/riscv: Add the tcg target registersAlistair Francis2018-12-251-0/+118
* tcg/riscv: Add the tcg-target.h fileAlistair Francis2018-12-251-0/+177