bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	tcg: Remove TCG_TARGET_CON_SET_H	Richard Henderson	2021-02-02	1	-1/+0
*	tcg/riscv: Split out constraint sets to tcg-target-con-set.h	Richard Henderson	2021-02-02	3	-60/+54
*	tcg: Remove TCG_TARGET_CON_STR_H	Richard Henderson	2021-02-02	1	-1/+0
*	tcg/riscv: Split out target constraints to tcg-target-con-str.h	Richard Henderson	2021-02-02	3	-39/+35
*	tcg: Remove movi and dupi opcodes	Richard Henderson	2021-01-13	1	-2/+0
*	tcg: Constify TCGLabelQemuLdst.raddr	Richard Henderson	2021-01-07	1	-2/+1
*	tcg: Constify tcg_code_gen_epilogue	Richard Henderson	2021-01-07	1	-2/+1
*	tcg: Remove TCG_TARGET_SUPPORT_MIRROR	Richard Henderson	2021-01-07	1	-1/+0
*	tcg/riscv: Support split-wx code generation	Richard Henderson	2021-01-07	2	-19/+24
*	tcg/riscv: Remove branch-over-branch fallback	Richard Henderson	2021-01-07	1	-50/+6
*	tcg/riscv: Fix branch range checks	Richard Henderson	2021-01-07	1	-13/+15
*	tcg: Add --accel tcg,split-wx property	Richard Henderson	2021-01-07	1	-0/+1
*	tcg: Adjust tb_target_set_jmp_target for split-wx	Richard Henderson	2021-01-07	1	-1/+1
*	tcg: Adjust tcg_register_jit for const	Richard Henderson	2021-01-07	1	-1/+1
*	tcg: Adjust tcg_out_call for const	Richard Henderson	2021-01-07	1	-3/+3
*	tcg: Move tcg epilogue pointer out of TCGContext	Richard Henderson	2021-01-07	1	-2/+2
*	tcg: Introduce INDEX_op_qemu_st8_i32	Richard Henderson	2021-01-07	1	-0/+1
*	Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...	Peter Maydell	2021-01-06	1	-5/+0
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\| *	util: Extract flush_icache_range to cacheflush.c	Richard Henderson	2021-01-02	1	-5/+0
* \|	tcg/riscv: Fix illegal shift instructions	Zihao Yu	2021-01-04	1	-6/+6
\|/
*	tcg: Remove TCG_CT_REG	Richard Henderson	2020-10-08	1	-2/+0
*	tcg: Drop union from TCGArgConstraint	Richard Henderson	2020-10-08	1	-7/+7
*	meson: rename included C source files to .c.inc	Paolo Bonzini	2020-08-21	1	-2/+2
*	tcg/riscv: Remove superfluous breaks	Liao Pingfang	2020-07-14	1	-2/+0
*	tcg: Search includes in the parent source directory	Philippe Mathieu-Daudé	2020-01-16	1	-2/+2
*	tcg: TCGMemOp is now accelerator independent MemOp	Tony Nguyen	2019-09-03	1	-10/+10
*	tcg/riscv: Fix RISC-VH host build failure	Alistair Francis	2019-07-09	1	-2/+2
*	cpu: Move the softmmu tlb to CPUNegativeOffsetState	Richard Henderson	2019-06-10	1	-24/+7
*	tcg: Create struct CPUTLB	Richard Henderson	2019-06-10	1	-10/+2
*	tcg: Return bool success from tcg_out_mov	Richard Henderson	2019-05-13	1	-2/+3
*	tcg: Restart TB generation after out-of-line ldst overflow	Richard Henderson	2019-04-24	1	-4/+12
*	tcg: Add INDEX_op_extract2_{i32,i64}	Richard Henderson	2019-04-24	1	-0/+2
*	cputlb: Remove static tlb sizing	Richard Henderson	2019-01-28	1	-1/+0
*	tcg/riscv: enable dynamic TLB sizing	Richard Henderson	2019-01-28	2	-71/+55
*	tcg: introduce dynamic TLB sizing	Emilio G. Cota	2019-01-28	1	-0/+1
*	tcg/riscv: Add the target init code	Alistair Francis	2018-12-25	1	-0/+31
*	tcg/riscv: Add the prologue generation and register the JIT	Alistair Francis	2018-12-25	1	-0/+111
*	tcg/riscv: Add the out op decoder	Alistair Francis	2018-12-25	1	-0/+496
*	tcg/riscv: Add direct load and store instructions	Alistair Francis	2018-12-25	1	-0/+158
*	tcg/riscv: Add slowpath load and store instructions	Alistair Francis	2018-12-25	1	-0/+256
*	tcg/riscv: Add branch and jump instructions	Alistair Francis	2018-12-25	1	-0/+145
*	tcg/riscv: Add the add2 and sub2 instructions	Alistair Francis	2018-12-25	1	-0/+55
*	tcg/riscv: Add the out load and store instructions	Alistair Francis	2018-12-25	1	-0/+65
*	tcg/riscv: Add the extract instructions	Alistair Francis	2018-12-25	1	-0/+34
*	tcg/riscv: Add the mov and movi instruction	Alistair Francis	2018-12-25	1	-0/+86
*	tcg/riscv: Add the relocation functions	Alistair Francis	2018-12-25	1	-0/+88
*	tcg/riscv: Add the instruction emitters	Alistair Francis	2018-12-25	1	-0/+48
*	tcg/riscv: Add the immediate encoders	Alistair Francis	2018-12-25	1	-0/+90
*	tcg/riscv: Add support for the constraints	Alistair Francis	2018-12-25	1	-0/+168
*	tcg/riscv: Add the tcg target registers	Alistair Francis	2018-12-25	1	-0/+118