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path: root/src/arch/riscv/core
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* [ioapi] Allow iounmap() to be called for port I/O addressesMichael Brown2025-11-051-5/+10
* [riscv] Correct page table stride calculationMichael Brown2025-10-271-1/+1
* [riscv] Ensure coherent DMA allocations do not cross cacheline boundariesMichael Brown2025-07-111-0/+15
* [riscv] Support the standard Svpbmt extension for page-based memory typesMichael Brown2025-07-111-0/+20
* [riscv] Create coherent DMA mapping of 32-bit address space on demandMichael Brown2025-07-112-36/+76
* [riscv] Use 1GB pages for I/O device mappingsMichael Brown2025-07-111-9/+9
* [riscv] Invalidate data cache on completed RX DMA buffersMichael Brown2025-07-101-5/+47
* [riscv] Add optimised TCP/IP checksummingMichael Brown2025-07-101-0/+138
* [riscv] Provide a DMA API implementation for RISC-V bare-metal systemsMichael Brown2025-07-092-9/+141
* [riscv] Support explicit cache management operations on I/O buffersMichael Brown2025-07-071-0/+256
* [riscv] Add support for detecting T-Head vendor extensionsMichael Brown2025-07-071-0/+65
* [riscv] Ignore riscv,isa property in favour of direct CSR testingMichael Brown2025-05-262-13/+5Star
* [riscv] Support mapping I/O devices outside of the identity mapMichael Brown2025-05-261-0/+227
* [riscv] Speed up memmove() when copying in forwards directionMichael Brown2025-05-211-47/+8Star
* [fdt] Allow for the existence of multiple device treesMichael Brown2025-03-282-4/+4
* [riscv] Check if seed CSR is accessible from S-modeMichael Brown2024-10-291-0/+7
* [sbi] Add support for running as a RISC-V SBI payloadMichael Brown2024-10-281-0/+45
* [riscv] Add missing volatile qualifiers on timer and seed CSR accessesMichael Brown2024-10-282-9/+11
* [riscv] Add support for the seed CSR as an entropy sourceMichael Brown2024-10-281-0/+110
* [riscv] Add support for RDTIME as a timer sourceMichael Brown2024-10-281-0/+193
* [riscv] Add support for checking CPU extensions reported via device treeMichael Brown2024-10-281-0/+100
* [crypto] Use constant-time big integer multiplicationMichael Brown2024-09-231-112/+0Star
* [riscv] Add support for the RISC-V CPU architectureMichael Brown2024-09-155-0/+605
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