| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | | | | clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled() | Gabriel Fernandez | 2017-09-01 | 1 | -6/+6 | |
| | * | | | | | | clk: uniphier: add PXs3 clock data | Masahiro Yamada | 2017-09-01 | 4 | -0/+46 | |
| | * | | | | | | clk: hi6220: change watchdog clock source | Leo Yan | 2017-09-01 | 1 | -3/+3 | |
| | * | | | | | | clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808 | Elaine Zhang | 2017-09-01 | 1 | -2/+2 | |
| | * | | | | | | clk: cs2000: Add cs2000_set_saved_rate | Gaku Inami | 2017-08-31 | 1 | -4/+10 | |
| | * | | | | | | clk: imx51: propagate rate across ipu_di*_sel | Lucas Stach | 2017-08-31 | 1 | -4/+4 | |
| | * | | | | | | Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kern... | Stephen Boyd | 2017-08-31 | 8 | -0/+1855 | |
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| | | * | | | | | | clk: sunxi-ng: Add sun4i/sun7i CCU driver | Priit Laes | 2017-08-24 | 7 | -0/+1853 | |
| | | * | | | | | | dt-bindings: List devicetree binding for the CCU of Allwinner A10 | Priit Laes | 2017-08-24 | 1 | -0/+1 | |
| | | * | | | | | | dt-bindings: List devicetree binding for the CCU of Allwinner A20 | Priit Laes | 2017-08-24 | 1 | -0/+1 | |
| | * | | | | | | | clk: sunxi: fix uninitialized access | Arnd Bergmann | 2017-08-31 | 1 | -0/+4 | |
| | * | | | | | | | clk: versatile: make clk_ops const | Bhumika Goyal | 2017-08-31 | 1 | -1/+1 | |
| | * | | | | | | | ARC: clk: introduce HSDK pll driver | Eugeniy Paltsev | 2017-08-31 | 5 | -0/+473 | |
| | * | | | | | | | clk: zte: constify clk_div_table | Arvind Yadav | 2017-08-31 | 1 | -3/+3 | |
| | * | | | | | | | clk: imx: constify clk_div_table | Arvind Yadav | 2017-08-31 | 5 | -12/+12 | |
| | * | | | | | | | clk: uniphier: add ethernet clock control support | Kunihiko Hayashi | 2017-08-31 | 1 | -0/+10 | |
| | * | | | | | | | clk: gemini: hands off PCI OE bit | Linus Walleij | 2017-08-31 | 1 | -7/+0 | |
| | * | | | | | | | clk: ux500: prcc: constify clk_ops. | Arvind Yadav | 2017-08-31 | 1 | -3/+3 | |
| | * | | | | | | | clk: ux500: sysctrl: constify clk_ops. | Arvind Yadav | 2017-08-31 | 1 | -4/+4 | |
| | * | | | | | | | clk: ux500: prcmu: constify clk_ops. | Arvind Yadav | 2017-08-31 | 1 | -7/+7 | |
| | * | | | | | | | clk: msm8996-gcc: add missing smmu clks | Srinivas Kandagatla | 2017-08-24 | 2 | -0/+30 | |
| | * | | | | | | | clk: tegra: Fix Tegra210 PLLU initialization | Alex Frid | 2017-08-24 | 1 | -2/+4 | |
| | * | | | | | | | clk: tegra: Correct Tegra210 UTMIPLL poweron delay | Alex Frid | 2017-08-24 | 1 | -3/+3 | |
| | * | | | | | | | clk: tegra: Fix T210 PLLRE registration | Alex Frid | 2017-08-24 | 1 | -20/+1 | |
| | * | | | | | | | clk: tegra: Update T210 PLLSS (D2/DP) registration | Alex Frid | 2017-08-24 | 1 | -39/+9 | |
| | * | | | | | | | clk: tegra: Re-factor T210 PLLX registration | Alex Frid | 2017-08-24 | 4 | -49/+10 | |
| | * | | | | | | | clk: tegra: don't warn for pll_d2 defaults unnecessarily | Peter De Schrijver | 2017-08-24 | 1 | -2/+4 | |
| | * | | | | | | | clk: tegra: change post IDDQ release delay to 5us | Peter De Schrijver | 2017-08-24 | 1 | -1/+1 | |
| | * | | | | | | | clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C | Alex Frid | 2017-08-24 | 1 | -1/+2 | |
| | * | | | | | | | clk: tegra: Fix T210 effective NDIV calculation | Alex Frid | 2017-08-24 | 1 | -4/+5 | |
| | * | | | | | | | clk: tegra: Init cfg structure in _get_pll_mnp | Peter De Schrijver | 2017-08-24 | 1 | -0/+2 | |
| | * | | | | | | | clk: tegra210: remove non-existing VFIR clock | Peter De Schrijver | 2017-08-24 | 1 | -1/+0 | |
| | * | | | | | | | clk: tegra: disable SSC for PLL_D2 | Peter De Schrijver | 2017-08-24 | 1 | -1/+1 | |
| | * | | | | | | | clk: tegra: Enable PLL_SS for Tegra210 | Peter De Schrijver | 2017-08-24 | 1 | -1/+1 | |
| | * | | | | | | | clk: tegra: fix SS control on PLL enable/disable | Peter De Schrijver | 2017-08-24 | 1 | -20/+24 | |
| | * | | | | | | | clk: qcom: msm8916: Fix bimc gpu clock ops | Georgi Djakov | 2017-08-24 | 1 | -1/+1 | |
| | * | | | | | | | clk: ti: make clk_ops const | Bhumika Goyal | 2017-08-24 | 3 | -4/+4 | |
| | * | | | | | | | Merge tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/... | Stephen Boyd | 2017-08-24 | 15 | -85/+674 | |
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| | | * | | | | | | | clk: renesas: r8a7796: Add USB3.0 clock | Hiromitsu Yamasaki | 2017-08-17 | 1 | -0/+1 | |
| | | * | | | | | | | clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY | Yoshihiro Shimoda | 2017-08-17 | 4 | -0/+249 | |
| | | * | | | | | | | clk: renesas: cpg-mssr: Add R8A77995 support | Geert Uytterhoeven | 2017-08-16 | 6 | -1/+251 | |
| | | * | | | | | | | clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks | Geert Uytterhoeven | 2017-08-16 | 2 | -1/+26 | |
| | | * | | | | | | | clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3 | Geert Uytterhoeven | 2017-08-16 | 4 | -37/+41 | |
| | | * | | | | | | | clk: renesas: Add r8a77995 CPG Core Clock Definitions | Geert Uytterhoeven | 2017-08-16 | 1 | -0/+57 | |
| | | * | | | | | | | clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table | Wolfram Sang | 2017-07-19 | 1 | -26/+20 | |
| | | * | | | | | | | clk: renesas: rcar-gen3-cpg: Drop superfluous variable | Wolfram Sang | 2017-07-19 | 1 | -2/+1 | |
| | | * | | | | | | | clk: renesas: Allow compile-testing of all (sub)drivers | Geert Uytterhoeven | 2017-07-17 | 1 | -19/+19 | |
| | | * | | | | | | | clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks | Geert Uytterhoeven | 2017-07-17 | 1 | -0/+7 | |
| | | * | | | | | | | clk: renesas: div6: Document fields used for parent selection | Geert Uytterhoeven | 2017-07-17 | 1 | -0/+3 | |
| | * | | | | | | | | clk: rockchip: Mark rockchip_fractional_approximation static | Stephen Boyd | 2017-08-24 | 1 | -1/+1 | |
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index : openslx/kernel-qcow2-linux.git | |
| In-kernel qcow2 (Kernel part) | OpenSLX |
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