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path: root/drivers/clk/tegra/clk-tegra124.c
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* clk: tegra: Make vde a child of pll_c3Thierry Reding2018-07-091-1/+1
| | | | | | | | | | The current default is to leave the VDE clock's parent at the default, which is clk_m. However, that is not a configuration that will allow the VDE to function. Reparent it to pll_c3 instead to make sure the hardware can actually decode video content. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: tegra: Make vic03 a child of pll_c3Thierry Reding2018-07-091-0/+1
| | | | | | | | | By default, the vic03 clock is a child of pll_m but that runs at 924 MHz which is too fast for VIC. Make vic03 a child of pll_c3 by default so it will run at a supported frequency. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko2018-05-181-1/+1
| | | | | | | | | | | | | CDEV1 and CDEV2 clocks are a bit special case, their parent clock is created by the pinctrl driver. It should be possible for clk user to request these clocks before pinctrl driver got probed and hence user will get an orphaned clock. That might be undesirable because user may expect parent clock to be enabled by the child, so let's return -EPROBE_DEFER till parent clock appears. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Specify VDE clock rateDmitry Osipenko2018-03-121-1/+1
| | | | | | | | | | Currently VDE clock rate is determined by clock config left from bootloader, let's not rely on it and explicitly specify the clock rate in the CCF driver. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko2018-03-121-4/+3Star
| | | | | | | | | | Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks as critical. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: <stable@vger.kernel.org> # v4.16 Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Add CEC clockPeter De Schrijver2017-03-201-0/+1
| | | | | | | | | This clock is used to clock the HDMI CEC interface. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker2016-06-301-154/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the UTMI PLL initialization code form clk-tegra<chip>.c files into clk-pll.c. UTMI PLL was being configured and set in HW control right after registration. However, when the clock init_table is processed and child clks of PLLU are enabled, it will call in and enable PLLU as well, and initiate SW enabling sequence even though PLLU is already in HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status. Doing the initialization once during pllu_enable means we configure it properly into HW control. A side effect of the commonization/localization of the UTMI PLL init code, is that it corrects some errors that were present for earlier generations. For instance, in clk-tegra124.c, it used to have: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) when the correct shift to use is present in the new version: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) which matches the Tegra124 TRM register definition. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> [rklein: Merged in some later fixes for potential deadlocks] Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding: coding style bike-shedding, remove unused variable] Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding2016-04-281-0/+4
| | | | | | | | The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have a gate bit in the peripheral clock registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein2015-11-201-30/+63
| | | | | | | | | | | | | | | | | | This removes the conversion from pdiv to hw, which is already taken care of by _get_table_rate before this code is run. This avoids incorrectly converting pdiv to hw twice and getting the wrong hw value. Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while setting all the other fields. In order to prevent regressions on earlier SoC generations, all of the frequency tables need to be updated so that they contain the actual divider values. If they contain hardware values these would be converted to hardware values again, yielding the wrong value. Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding@nvidia.com: fix regressions on earlier SoC generations] Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein2015-11-201-9/+15
| | | | | | | | | | | | SoC specific drivers should define the appropriate flags for each PLL rather than relying on the registration functions to automatically set flags on their behalf. This will properly allow for changes between SoC generations where flags might be different and allow sharing the same logic functions. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Constify pdiv-to-hw mappingsThierry Reding2015-11-201-5/+5
| | | | | | This is static data that is never modified, so make it const. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Format tables consistentlyThierry Reding2015-11-181-184/+186
| | | | | | | Use spaces around { and } and pad values so that the cells are properly aligned. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Miscellaneous coding style cleanupsThierry Reding2015-11-181-3/+3
| | | | | | | | | Use unsigned int for loop variables that can never become negative and remove a couple of gratuitous blank lines. Also use single spaces around operators and use a single space instead of a tab to separate comments from code. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding2015-11-181-1/+1
| | | | | | | | | The OSC_FREQ field of the OSC_CTRL register uses the value 12 for an oscillator frequency of 26 MHz, not 260 MHz. This isn't really critical because I don't think boards with such an oscillator have ever existed, much less been supported upstream. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein2015-10-201-1/+7
| | | | | | | | | | | tegra_audio_clk_init was written expecting a single PLL to be passed in directly. Change this to accept an array which will allow for supporting multiple plls and specifying specific data about them, like their parent, which may change over time. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Fix some static checker problemsStephen Boyd2015-08-261-4/+4
| | | | | | | | | | | | | The latest Tegra clk pull had some problems. Fix them. drivers/clk/tegra/clk-tegra124.c:1450:6: warning: symbol 'tegra124_clock_assert_dfll_dvco_reset' was not declared. Should it be static? drivers/clk/tegra/clk-tegra124.c:1466:6: warning: symbol 'tegra124_clock_deassert_dfll_dvco_reset' was not declared. Should it be static? drivers/clk/tegra/clk-tegra124.c:1476:5: warning: symbol 'tegra124_reset_assert' was not declared. Should it be static? drivers/clk/tegra/clk-tegra124.c:1486:5: warning: symbol 'tegra124_reset_deassert' was not declared. Should it be static? drivers/clk/tegra/clk-dfll.c:590 dfll_load_i2c_lut() warn: inconsistent indenting drivers/clk/tegra/clk-dfll.c:1448 dfll_build_i2c_lut() warn: unsigned 'td->i2c_lut[0]' is never less than zero. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'tegra-for-4.3-clk' of ↵Stephen Boyd2015-08-261-0/+82
|\ | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.3-rc1 This contains the DFLL driver needed to implement CPU frequency scaling on Tegra.
| * clk: tegra: Save/restore CCLKG_BURST_POLICY on suspendTuomas Tynkkynen2015-07-161-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Save and restore this register since the LP1 restore assembly routines fiddle with it. Otherwise the CPU would keep running on PLLX after resume from suspend even when DFLL was the original clocksource. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Add DFLL DVCO reset control for Tegra124Paul Walmsley2015-07-161-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete. Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and saving hours of debugging time. Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> [ttynkkynen: ported to tegra124 from tegra114] Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> [mikko.perttunen: ported to special reset callback] Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | clk: tegra: Properly include clk.hStephen Boyd2015-07-201-1/+0Star
|/ | | | | | | | | | | Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. Also add in a clkdev.h include that was missing in a file using clkdev APIs. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Set the EMC clock as the parent of the MC clockTomeu Vizoso2015-05-131-12/+1Star
| | | | | | | On Tegra124, as we now have a proper driver for the EMC. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Add EMC clock driverMikko Perttunen2015-05-131-1/+4
| | | | | | | | | | | | The driver is currently only tested on Tegra124 Jetson TK1, but should work with other Tegra124 boards, provided that correct EMC tables are provided through the device tree. Older chip models have differing timing change sequences, so they are not currently supported. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> [treding@nvidia.com: use more consistent function names] Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Remove old Tegra124 EMC clockMikko Perttunen2015-05-131-1/+0Star
| | | | | | | | This clock has never been able to do anything. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Use the proper parent for plld_dsiThierry Reding2015-04-101-6/+8
| | | | | | | | | The current parent, plld_out0, does not exist. The proper name is pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to be more consistent with other clock names. Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux") Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Model oscillator as clockThierry Reding2015-04-101-1/+2
| | | | | | | | | | | | | | | | Currently the Tegra clock driver simplifies the clock tree somewhat by taking advantage of the fact that clk_m runs at the same frequency as the oscillator. While that's true on all currently supported SoCs, it does not apply to Tegra210 anymore. On Tegra210 clk_m is typically divided down from the oscillator frequency. To support that setup, add a separate clock for the oscillator that both clk_m and pll_ref derive from. Modify the tegra_osc_clk_init() function to take an additional divider parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210 will read the divider from a register in the clock & reset controller. Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Enable HDA to HDMI clocks on Tegra124Dylan Reid2015-04-101-0/+5
| | | | | | | | | | Add the clocks used for HDMI audio played through the HDA controller. Initialize the codec clock to 48Mhz and the HDA clock to 102MHz per the TRM. Signed-off-by: Dylan Reid <dgreid@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang2015-02-021-20/+16Star
| | | | | | | | | | | | | PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock. So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
* clk: tegra: Add support for the Tegra132 CAR IP blockPaul Walmsley2015-02-021-9/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This patch mostly deals with the small differences. Since Tegra132 contains many of the same PLL clock sources used on Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when the kernel is configured to include Tegra132 support. This patch is based on several patches from others: 1. a patch from Peter De Schrijver: http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html 2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on Tegra132"), and 3. a patch from Allen Martin ("clk: Enable tegra clock driver for tegra132"). Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Bill Huang <bilhuang@nvidia.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra124: Add init data for dsi lp clocksSean Paul2015-02-021-0/+2
| | | | | | | | | | | | Set the parent of the dsi lp clocks to pll_p and the rate to 68MHz. The default parent is clk_m and rate is 12MHz, this is too slow to receive data from the peripheral. Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz will suffice. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: Implement memory-controller clockThierry Reding2014-11-261-1/+6
| | | | | | | | | The memory controller clock runs either at half or the same frequency as the EMC clock. Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* clk: tegra124: Add PLL_M_UD and PLL_C_UD clocksMikko Perttunen2014-09-181-0/+8
| | | | | | These clocks are used as parents for some EMC timings. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
* clk: tegra124: init table updatesPeter De Schrijver2014-06-271-0/+6
| | | | | | | | Ensure some clocks critical for system operation are always. Also enable csite for JTAG debugging and set the tsensor and soc_therm clock frequencies for the upcoming soctherm driver. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: Add SATA clocks to Tegra124 initialization tableMikko Perttunen2014-06-251-0/+2
| | | | | | | | This adds two clocks, SATA and SATA_OOB, to the Tegra124 clock initialization table. The clocks are needed for working SATA support. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: fix vi_sensor clocks on Tegra124Peter De Schrijver2014-06-251-1/+1
| | | | | | | | vi_sensor and vi_sensor2 have a wrong hw clkid on Tegra124. Fix this by correcting the hw clkid for Tegra124 and creating the Tegra114 vi_sensor clock from its own data. Tegra124 was also using the wrong internal clock id. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: Initialize xusb clocksAndrew Bresticker2014-05-231-0/+6
| | | | | | | | | Initialize the XUSB-related clocks with appropriate parents and rates for both Tegra114 and Tegra124. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker2014-05-231-10/+5Star
| | | | | | | | | | | Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: remove non-existent clocksStephen Warren2014-04-241-3/+0Star
| | | | | | | | | The Tegra124 clock driver currently provides 3 clocks that don't actually exist; 2 for NAND and one for UART5/UARTE. Delete these. Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* clk: tegra124: remove gr2d and gr3d clocksPeter De Schrijver2014-02-201-2/+0Star
| | | | | | | Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the vic03 and gpu clocks respectively. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker2014-02-171-4/+4
| | | | | | | | The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
* clk: tegra: fix host1x clock on Tegra124Mark Zhang2014-02-171-1/+1
| | | | | | | | | The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents. Change thte id to tegra_clk_host1x_8 so that the correct clock gets registered. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
* clk: tegra: PLLD2 fixes for hdmiDavid Ung2014-02-171-8/+7Star
| | | | | | | Set correct pll_d2_out0 divider and correct the p div values for pll_d2. Signed-off-by: David Ung <davidu@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
* clk: tegra: Fix PLLD mnp tableRhyland Klein2014-02-171-1/+10
| | | | | | | | PLLD was using the same mnp table as PLLP. Fix it to use its own table which is different from PLLP's. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
* clk: tegra: Fix PLLP rate tableGabe Black2014-02-171-5/+5
| | | | | | | | | This table had settings for 216MHz, but PLLP is (and is supposed to be) configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is not set, the kernel will panic in clk_pll_recalc_rate(). Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
* clk: tegra: implement a reset driverStephen Warren2013-12-121-1/+1
| | | | | | | | | | | | | The Tegra CAR module implements both a clock and reset controller. So far, the driver exposes the clock feature via the common clock API and the reset feature using a custom API. This patch adds an implementation of the common reset framework API (include/linux/reset*.h). The legacy reset implementation will be removed once all drivers have been converted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
* clk: tegra: add FUSE clock deviceAlexandre Courbot2013-11-261-0/+1
| | | | | | | This clock is needed to ensure the FUSE registers can be accessed without freezing the system. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* clk: tegra124: add suspend/resume function for tegra_cpu_car_opsJoseph Lo2013-11-261-0/+27
| | | | | | | | | | Adding suspend/resume function for tegra_cpu_car_ops. We only save and restore the setting of the clock of CoreSight. Other clocks still need to be taken care by clock driver. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_opsJoseph Lo2013-11-261-0/+26
| | | | | | | | | Hook the functions for CPU hotplug support. After the CPU is hot unplugged, the flow controller will handle to clock gate the CPU clock. But still need to implement an empty function to avoid warning message. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com>
* clk: tegra124: Add support for Tegra124 clocksPeter De Schrijver2013-11-261-0/+1370
Implement clock support for Tegra124. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-16 09:52:59 +0200