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* Merge branch 'pci/trivial'Bjorn Helgaas2019-07-136-6/+6
|\ | | | | | | | | | | | | - Fix typos and whitespace errors (Bjorn Helgaas) * pci/trivial: PCI: Fix typos and whitespace errors
| * PCI: Fix typos and whitespace errorsBjorn Helgaas2019-07-096-6/+6
| | | | | | | | | | | | | | | | Fix typos in drivers/pci. Comment and whitespace changes only. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
* | Merge branch 'remotes/lorenzo/pci/xilinx'Bjorn Helgaas2019-07-131-6/+5Star
|\ \ | | | | | | | | | | | | | | | | | | - Fix Xilinx NWL multi-MSI vector aliasing issue (Bharat Kumar Gogada) * remotes/lorenzo/pci/xilinx: PCI: xilinx-nwl: Fix Multi MSI data programming
| * | PCI: xilinx-nwl: Fix Multi MSI data programmingBharat Kumar Gogada2019-06-261-6/+5Star
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the PCI Local Bus specification Revision 3.0, section 6.8.1.3 (Message Control for MSI), endpoints that are Multiple Message Capable as defined by bits [3:1] in the Message Control for MSI can request a number of vectors that is power of two aligned. As specified in section 6.8.1.6 "Message data for MSI", the Multiple Message Enable field (bits [6:4] of the Message Control register) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. The MSI controller in the Xilinx NWL PCIe controller supports a number of MSI vectors specified through a bitmap and the hwirq number for an MSI, that is the value written in the MSI data TLP is determined by the bitmap allocation. For instance, in a situation where two endpoints sitting on the PCI bus request the following MSI configuration, with the current PCI Xilinx bitmap allocation code (that does not align MSI vector allocation on a power of two boundary): Endpoint #1: Requesting 1 MSI vector - allocated bitmap bits 0 Endpoint #2: Requesting 2 MSI vectors - allocated bitmap bits [1,2] The bitmap value(s) corresponds to the hwirq number that is programmed into the Message Data for MSI field in the endpoint MSI capability and is detected by the root complex to fire the corresponding MSI irqs. The value written in Message Data for MSI field corresponds to the first bit allocated in the bitmap for Multi MSI vectors. The current Xilinx NWL MSI allocation code allows a bitmap allocation that is not a power of two boundaries, so endpoint #2, is allowed to toggle Message Data bit[0] to differentiate between its two vectors (meaning that the MSI data will be respectively 0x0 and 0x1 for the two vectors allocated to endpoint #2). This clearly aliases with the Endpoint #1 vector allocation, resulting in a broken Multi MSI implementation. Update the code to allocate MSI bitmap ranges with a power of two alignment, fixing the bug. Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller") Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
* | Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas2019-07-131-82/+507
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Reorganize Tegra AFI/PHY/REFCLK/etc functions (Manikanta Maddireddy) - Mask Tegra AFI_INTR in runtime suspend (Manikanta Maddireddy) - Fix Tegra AFI/PCIe powerup sequence (Manikanta Maddireddy) - Add Tegra124, Tegra132, Tegra210, and Tegra186 support for Gen2 link speed (Manikanta Maddireddy) - Advertise Tegra AER support (Manikanta Maddireddy) - Program Tegra210 UPHY settings (Manikanta Maddireddy) - Enable Tegra opportunistic UpdateFC and ACK (Manikanta Maddireddy) - Disable Tegra AFI dynamic clock gating (Manikanta Maddireddy) - Process Tegra pending DLL transactions before entering L1 or L2 to prevent receiver errors (Manikanta Maddireddy) - Enable Tegra xclk clock clamping in L1 (Manikanta Maddireddy) - Increase Tegra deskew retry time (Manikanta Maddireddy) - Work around Tegra hardware RAW erratum (Manikanta Maddireddy) - Update Tegra210 flow control timer frequency (Manikanta Maddireddy) - Work around Tegra Gen1/Gen2 link number negotiation issue (Manikanta Maddireddy) - Work around Tegra PLLE power down issue (Manikanta Maddireddy) - Program Tegra20 to support cacheable upstream transactions (Manikanta Maddireddy) - Log Tegra PRSNT_SENSE_IRQ as debug, not err (Manikanta Maddireddy) - Add register offset for third Root Port on Tegra186 and Tegra30 (Manikanta Maddireddy) - Document Tegra PCIe DPD pinctrl property (Manikanta Maddireddy) - Put Tegra PEX CLK & BIAS pads in DPD mode to reduce power usage when powergated (Manikanta Maddireddy) - Add generic DT binding for "reset-gpios" property (Manikanta Maddireddy) - Add Tegra support for GPIO-based PERST# (Manikanta Maddireddy) - Enable Relaxed Ordering only for Tegra20 & Tegra30 (Vidya Sagar) * remotes/lorenzo/pci/tegra: PCI: tegra: Enable Relaxed Ordering only for Tegra20 & Tegra30 PCI: tegra: Change link retry log level to debug PCI: tegra: Add support for GPIO based PERST# PCI: Add DT binding for "reset-gpios" property PCI: tegra: Put PEX CLK & BIAS pads in DPD mode dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct PCI: tegra: Change PRSNT_SENSE IRQ log to debug PCI: tegra: Program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20 PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal PCI: tegra: Set target speed as Gen1 before starting LTSSM PCI: tegra: Update flow control timer frequency in Tegra210 PCI: tegra: Add SW fixup for RAW violations PCI: tegra: Increase the deskew retry time PCI: tegra: Enable PCIe xclk clock clamping PCI: tegra: Process pending DLL transactions before entering L1 or L2 PCI: tegra: Disable AFI dynamic clock gating PCI: tegra: Enable opportunistic UpdateFC and ACK PCI: tegra: Program UPHY electrical settings for Tegra210 PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability PCI: tegra: Add PCIe Gen2 link speed support PCI: tegra: Fix PCIe host power up sequence PCI: tegra: Mask AFI_INTR in runtime suspend PCI: tegra: Rearrange Tegra PCIe driver functions PCI: tegra: Handle failure cases in tegra_pcie_power_on() soc/tegra: pmc: Export tegra_powergate_power_on()
| * | PCI: tegra: Enable Relaxed Ordering only for Tegra20 & Tegra30Vidya Sagar2019-07-051-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI Tegra controller conversion to a device tree configurable driver in commit d1523b52bff3 ("PCI: tegra: Move PCIe driver to drivers/pci/host") implied that code for the driver can be compiled in for a kernel supporting multiple platforms. Unfortunately, a blind move of the code did not check that some of the quirks that were applied in arch/arm (eg enabling Relaxed Ordering on all PCI devices - since the quirk hook erroneously matches PCI_ANY_ID for both Vendor-ID and Device-ID) are now applied in all kernels that compile the PCI Tegra controlled driver, DT and ACPI alike. This is completely wrong, in that enablement of Relaxed Ordering is only required by default in Tegra20 platforms as described in the Tegra20 Technical Reference Manual (available at https://developer.nvidia.com/embedded/downloads#?search=tegra%202 in Section 34.1, where it is mentioned that Relaxed Ordering bit needs to be enabled in its root ports to avoid deadlock in hardware) and in the Tegra30 platforms for the same reasons (unfortunately not documented in the TRM). There is no other strict requirement on PCI devices Relaxed Ordering enablement on any other Tegra platforms or PCI host bridge driver. Fix this quite upsetting situation by limiting the vendor and device IDs to which the Relaxed Ordering quirk applies to the root ports in question, reported above. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> [lorenzo.pieralisi@arm.com: completely rewrote the commit log/fixes tag] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Change link retry log level to debugManikanta Maddireddy2019-07-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver checks for link up three times before giving up, each retry attempt is printed as an error. Letting users know that PCIe link is down and in the process of being brought up again is for debug, not an error condition. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Add support for GPIO based PERST#Manikanta Maddireddy2019-07-051-6/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra PCIe has fixed per port SFIO line to signal PERST#, which can be controlled by AFI port register. However, if a platform routes a different GPIO to the PCIe slot, then port register cannot control it. Add support for GPIO based PERST# signal for such platforms. GPIO number comes from per port PCIe device tree node. PCIe driver probe doesn't fail if per port "reset-gpios" property is not populated, so platforms that require this workaround must make sure that the DT property is not missed in the corresponding device tree. Link: https://lore.kernel.org/linux-pci/20190705084850.30777-1-jonathanh@nvidia.com/ Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> [lorenzo.pieralisi@arm.com: squashed in fix in Link] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Put PEX CLK & BIAS pads in DPD modeManikanta Maddireddy2019-06-201-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Tegra210 AFI design has clamp value for the BIAS pad as 0, which keeps the bias pad in non power down mode. This is leading to power consumption of 2 mW in BIAS pad, even if the PCIe partition is powergated. To avoid unnecessary power consumption, put PEX CLK & BIAS pads in deep power down mode when PCIe partition is power gated. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC structManikanta Maddireddy2019-06-201-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra186 and Tegra30 have three PCIe root ports. AFI_PEX2_CTRL register is defined for third root port. Offset of this register in Tegra186 is different from Tegra30, so add the offset as part of SoC data structure. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Change PRSNT_SENSE IRQ log to debugManikanta Maddireddy2019-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PRSNT_MAP bit field is programmed to update the slot present status. PRSNT_SENSE IRQ is triggered when this bit field is programmed, which is not an error. Add a new if condition to trap PRSNT_SENSE code and print it with debug log level. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20Manikanta Maddireddy2019-06-201-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cacheable upstream transactions are supported in Tegra20 and Tegra186 only. AFI_CACHE_BAR_{0,1}_{ST,SZ} registers are available in Tegra20 to support cacheable upstream transactions. In Tegra186, AFI_AXCACHE register is defined instead of AFI_CACHE_BAR_{0,1}_{ST,SZ} to be in line with its memory subsystem design. Therefore, program AFI_CACHE_BAR_{0,1}_{ST,SZ} registers only for Tegra20. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Fix PLLE power down issue due to CLKREQ# signalManikanta Maddireddy2019-06-201-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable controllers which failed to bring the link up and configure CLKREQ# signals of these controllers as GPIO. This is required to avoid CLKREQ# signal of inactive controllers interfering with PLLE power down sequence. PCIE_CLKREQ_GPIO bits are defined only in Tegra186, however programming these bits in other SoCs doesn't cause any side effects. Program these bits for all Tegra SoCs to avoid a conditional check. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Set target speed as Gen1 before starting LTSSMManikanta Maddireddy2019-06-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe link up fails with few legacy endpoints if root port advertises both Gen-1 and Gen-2 speeds in Tegra. This is because link number negotiation fails if both Gen1 & Gen2 are advertised. Tegra doesn't retry link up by advertising only Gen1. Hence, the strategy followed here is to initially advertise only Gen-1 and after link is up, retrain link to Gen-2 speed. Tegra doesn't support HW autonomous speed change. Link comes up in Gen1 even if Gen2 is advertised, so there is no downside of this change. This behavior is observed with following two PCIe devices on Tegra: - Fusion HDTV 5 Express card - IOGear SIL - PCIE - SATA card Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Update flow control timer frequency in Tegra210Manikanta Maddireddy2019-06-201-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recommended UpdateFC threshold in Tegra210 is 0x60 for best performance of x1 link. Setting this to 0x60 provides the best balance between number of UpdateFC packets and read data sent over the link. UpdateFC timer frequency is equal to twice the value of register content in nsec, i.e (2 * 0x60) = 192 nsec. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Add SW fixup for RAW violationsManikanta Maddireddy2019-06-201-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The logic which blocks read requests till AFI gets ACK for all outstanding writes from memory controller does not behave correctly when number of outstanding writes become more than 32 in Tegra124 and Tegra132. SW fixup is to prevent writes from accumulating more than 32 by: - limiting outstanding posted writes to 14 - modifying Gen1 and Gen2 UpdateFC timer frequency UpdateFC timer frequency is equal to twice the value of register content in nsec. These settings are recommended after stress testing with different values. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Increase the deskew retry timeManikanta Maddireddy2019-06-201-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes link speed change from Gen2 to Gen1 fails due to instability in deskew logic on lane-0 in Tegra210. Increase the deskew retry time to resolve this issue. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Enable PCIe xclk clock clampingManikanta Maddireddy2019-06-201-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable xclk clock clamping when entering L1. Clamp threshold will determine the time spent waiting for clock module to turn on xclk after signaling it. Default threshold value in Tegra124 and Tegra210 is not enough to turn on xclk clock. Increase the clamp threshold to meet the clock module timing in Tegra124 and Tegra210. Default threshold value is enough in Tegra20, Tegra30 and Tegra186. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Process pending DLL transactions before entering L1 or L2Manikanta Maddireddy2019-06-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PM message are truncated while entering L1 or L2, which is resulting in receiver errors. Set the required bit to finish processing DLLP before link enter L1 or L2. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Disable AFI dynamic clock gatingManikanta Maddireddy2019-06-201-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Outstanding write counter in AFI is used to generate idle signal to dynamically gate the AFI clock. When there are 32 outstanding writes from AFI to memory, the outstanding write counter overflows and indicates that there are "0" outstanding write transactions. When memory controller is under heavy load, write completions to AFI gets delayed and AFI write counter overflows. This causes AFI clock gating even when there are outstanding transactions towards memory controller resulting in a system hang. Disable dynamic clock gating of AFI clock to avoid system hang. CLKEN_OVERRIDE bit is not defined in Tegra20 and Tegra30, however programming this bit doesn't cause any side effects. Program this bit for all Tegra SoCs to avoid conditional check. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Enable opportunistic UpdateFC and ACKManikanta Maddireddy2019-06-201-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable opportunistic UpdateFC and ACK to allow data link layer send pending ACKs and UpdateFC packets when link is idle instead of waiting for timers to expire. This improves the PCIe performance due to better utilization of PCIe bandwidth. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Program UPHY electrical settings for Tegra210Manikanta Maddireddy2019-06-201-0/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UPHY electrical programming guidelines are documented in Tegra210 TRM. Program these electrical settings for proper eye diagram in Gen1 and Gen2 link speeds. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capabilityManikanta Maddireddy2019-06-201-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | Default root port setting hides AER capability. This patch enables the advertisement of AER capability by root port. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Add PCIe Gen2 link speed supportManikanta Maddireddy2019-06-201-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra124, Tegra132, Tegra210 and Tegra186 support Gen2 link speed. After PCIe link is up in Gen1, set target link speed as Gen2 and retrain link. Link switches to Gen2 speed if Gen2 capable end point is connected, otherwise the link stays in Gen1. Per PCIe 4.0r0.9 sec 7.6.3.7 implementation note, driver needs to wait for PCIe LTSSM to come back from recovery before retraining the link. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Fix PCIe host power up sequenceManikanta Maddireddy2019-06-201-22/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe host power up sequence requires to program AFI(AXI to FPCI bridge) registers first and then PCIe registers, otherwise AFI register settings may not latch to PCIe IP. PCIe root port starts LTSSM as soon as PCIe xrst is deasserted. So deassert PCIe xrst after programming PCIe registers. Modify PCIe power up sequence as follows: - Power ungate PCIe partition - Enable AFI clock - Deassert AFI reset - Program AFI registers - Enable PCIe clock - Deassert PCIe reset - Program PCIe PHY - Program PCIe pad control registers - Program PCIe root port registers - Deassert PCIe xrst to start LTSSM Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Mask AFI_INTR in runtime suspendManikanta Maddireddy2019-06-201-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AFI_INTR is unmasked in tegra_pcie_enable_controller(), mask it to avoid unwanted interrupts raised by AFI after pex_rst is asserted. The following sequence triggers such scenario: - tegra_pcie_remove() triggers runtime suspend - pex_rst is asserted in runtime suspend - PRSNT_MAP bit field in RP_PRIV_MISC register changes from EP_PRSNT to EP_ABSNT - This is sensed by AFI and triggers "Slot present pin change" interrupt - tegra_pcie_isr() function accesses AFI register when runtime suspend is going through power off sequence Resulting faulty backtrace: rmmod pci-tegra pci_generic_config_write32: 108 callbacks suppressed pci_bus 0002:00: 2-byte config write to 0002:00:02.0 offset 0x4c may corrupt adjacent RW1C bits pci_bus 0002:00: 2-byte config write to 0002:00:02.0 offset 0x9c may corrupt adjacent RW1C bits pci_bus 0002:00: 2-byte config write to 0002:00:02.0 offset 0x88 may corrupt adjacent RW1C bits pci_bus 0002:00: 2-byte config write to 0002:00:02.0 offset 0x90 may corrupt adjacent RW1C bits pci_bus 0002:00: 2-byte config write to 0002:00:02.0 offset 0x4 may corrupt adjacent RW1C bits igb 0002:04:00.1: removed PHC on enP2p4s0f1 igb 0002:04:00.0: removed PHC on enP2p4s0f0 pci_bus 0002:00: 2-byte config write to 0002:00:01.0 offset 0x4c may corrupt adjacent RW1C bits pci_bus 0002:00: 2-byte config write to 0002:00:01.0 offset 0x9c may corrupt adjacent RW1C bits pci_bus 0002:00: 2-byte config write to 0002:00:01.0 offset 0x88 may corrupt adjacent RW1C bits pci_bus 0002:00: 2-byte config write to 0002:00:01.0 offset 0x90 may corrupt adjacent RW1C bits pci_bus 0002:00: 2-byte config write to 0002:00:01.0 offset 0x4 may corrupt adjacent RW1C bits rcu: INFO: rcu_preempt self-detected stall on CPU SError Interrupt on CPU0, code 0xbf000002 -- SError CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 5.1.0-rc3-next-20190405-00027-gcd8110499e6f-dirty #42 Hardware name: NVIDIA Jetson TX1 Developer Kit (DT) pstate: 20000085 (nzCv daIf -PAN -UAO) pc : tegra_pcie_isr+0x58/0x178 [pci_tegra] lr : tegra_pcie_isr+0x40/0x178 [pci_tegra] sp : ffff000010003da0 x29: ffff000010003da0 x28: 0000000000000000 x27: ffff8000f9e61000 x26: ffff000010fbf420 x25: ffff000011427f93 x24: ffff8000fa600410 x23: ffff00001129d000 x22: ffff00001129d000 x21: ffff8000f18bf3c0 x20: 0000000000000070 x19: 00000000ffffffff x18: 0000000000000000 x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000 x14: ffff000008d40a48 x13: ffff000008d40a30 x12: ffff000008d40a20 x11: ffff000008d40a10 x10: ffff000008d40a00 x9 : ffff000008d409e8 x8 : ffff000008d40ae8 x7 : ffff000008d40ad0 x6 : ffff000010003e58 x5 : ffff8000fac00248 x4 : 0000000000000000 x3 : ffff000008d40b08 x2 : fffffffffffffff8 x1 : ffff000008d3f4e8 x0 : 00000000ffffffff Kernel panic - not syncing: Asynchronous SError Interrupt CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 5.1.0-rc3-next-20190405-00027-gcd8110499e6f-dirty #42 Hardware name: NVIDIA Jetson TX1 Developer Kit (DT) Call trace: dump_backtrace+0x0/0x158 show_stack+0x14/0x20 dump_stack+0xa8/0xcc panic+0x140/0x2f4 nmi_panic+0x6c/0x70 arm64_serror_panic+0x74/0x80 __pte_error+0x0/0x28 el1_error+0x84/0xf8 tegra_pcie_isr+0x58/0x178 [pci_tegra] __handle_irq_event_percpu+0x70/0x198 handle_irq_event_percpu+0x34/0x88 handle_irq_event+0x48/0x78 handle_fasteoi_irq+0xb4/0x190 generic_handle_irq+0x24/0x38 __handle_domain_irq+0x5c/0xb8 gic_handle_irq+0x58/0xa8 el1_irq+0xb8/0x180 cpuidle_enter_state+0x138/0x358 cpuidle_enter+0x18/0x20 call_cpuidle+0x1c/0x48 do_idle+0x230/0x2d0 cpu_startup_entry+0x20/0x28 rest_init+0xd4/0xe0 arch_call_rest_init+0xc/0x14 start_kernel+0x444/0x470 AFI_INTR is re-enabled on resume in tegra_pcie_pm_resume() through tegra_pcie_enable_controller(). Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> [lorenzo.pieralisi@arm.com: updated log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Rearrange Tegra PCIe driver functionsManikanta Maddireddy2019-06-201-40/+30Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra PCIe has register specifications for: - AXI to FPCI(AFI) bridge - Multiple PCIe root ports - PCIe PHY - PCIe pad control Rearrange Tegra PCIe driver functions so that each function programs the required module only. - tegra_pcie_enable_controller(): Program AFI module and enable PCIe controller - tegra_pcie_phy_power_on(): Bring up PCIe PHY - tegra_pcie_apply_pad_settings(): Program PCIe REFCLK pad settings - tegra_pcie_enable_ports(): Program each root port and bring up PCIe link Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * | PCI: tegra: Handle failure cases in tegra_pcie_power_on()Manikanta Maddireddy2019-06-201-5/+21
| |/ | | | | | | | | | | | | | | | | Unroll the PCIe power on sequence if any one of the steps fails in tegra_pcie_power_on(). Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
* | Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas2019-07-131-61/+54Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move qcom driver to bulk clock API (Bjorn Andersson) - Add Qualcomm QCS404 PCIe controller support (Bjorn Andersson) - Ensure Qualcomm PERST is asserted for at least 100ms (Niklas Cassel) * remotes/lorenzo/pci/qcom: PCI: qcom: Ensure that PERST is asserted for at least 100 ms PCI: qcom: Add QCS404 PCIe controller support dt-bindings: PCI: qcom: Add QCS404 to the binding PCI: qcom: Use clk bulk API for 2.4.0 controllers
| * | PCI: qcom: Ensure that PERST is asserted for at least 100 msNiklas Cassel2019-05-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, there is only a 1 ms sleep after asserting PERST. Reading the datasheets for different endpoints, some require PERST to be asserted for 10 ms in order for the endpoint to perform a reset, others require it to be asserted for 50 ms. Several SoCs using this driver uses PCIe Mini Card, where we don't know what endpoint will be plugged in. The PCI Express Card Electromechanical Specification r2.0, section 2.2, "PERST# Signal" specifies: "On power up, the deassertion of PERST# is delayed 100 ms (TPVPERL) from the power rails achieving specified operating limits." Add a sleep of 100 ms before deasserting PERST, in order to ensure that we are compliant with the spec. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: stable@vger.kernel.org # 4.5+
| * | PCI: qcom: Add QCS404 PCIe controller supportBjorn Andersson2019-05-291-26/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QCS404 platform contains a PCIe version 2.4.0 controller and a Qualcomm PCIe2 PHY. The driver already supports version 2.4.0, for the IPQ4019, but this support touches clocks and resets related to the PHY as well and there's no upstream driver for the PHY. On QCS404 we must initialize the PHY, so a separate PHY driver is implemented to take care of this and the controller driver is updated to not require the PHY related resources. This is done by relying on the fact that operations in both the clock and reset framework are NOPs when passed NULL, so we can isolate this change to only the qcom_pcie_get_resources_2_4_0() function. For QCS404 we also need to enable the AHB (iface) clock, in order to access the register space of the controller, but as this is not part of the IPQ4019 DT binding this is only added for new users of the 2.4.0 controller. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
| * | PCI: qcom: Use clk bulk API for 2.4.0 controllersBjorn Andersson2019-05-291-37/+16Star
| |/ | | | | | | | | | | | | | | | | | | | | | | Before introducing the QCS404 platform, which uses the same PCIe controller as IPQ4019, migrate this to use the bulk clock API, in order to make the error paths slighly cleaner. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
* | Merge branch 'remotes/lorenzo/pci/mobiveil'Bjorn Helgaas2019-07-131-213/+312
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Unify mobiveil register accessors (Hou Zhiqiang) - Remove MSI_FLAG_MULTI_PCI_MSI since mobiveil hardware doesn't support Multiple MSI (Hou Zhiqiang) - Program outbound windows with base address from DT instead of assuming zero (Hou Zhiqiang) - Skip "safe" list traversal when it's unnecessary (Hou Zhiqiang) - Initialize WIN_NUM_0 explicitly for CFG outbound transactions (Hou Zhiqiang) - Use WIN_NUM_0 for MEM inbound transactions (Hou Zhiqiang) - Fix up mobiveil Class Code to PCI_CLASS_BRIDGE_PCI (Hou Zhiqiang) - Wait for link-up before enumerating devices, not while initializing host (Hou Zhiqiang) - Move IRQ chained handler setup out of DT code (Hou Zhiqiang) - Set primary/secondary/subordinate bus numbers (Hou Zhiqiang) - Fix "valid device" check to allow root bus device 0 to be multi-function (Hou Zhiqiang) - Make DT "gpio_slave" and "apb_csr" properties optional (Hou Zhiqiang) - Refactor MEM/IO outbound window initialization (Hou Zhiqiang) - Fix validity check for inbound/outbound window programming (Hou Zhiqiang) - Initialize and preserve window control bits (Hou Zhiqiang) - Fix 64-bit outbound window setup (both CPU and PCI addresses) (Hou Zhiqiang) - Move IO port setup to host init (Hou Zhiqiang) - Fix infinite loop in INTx ISR (Hou Zhiqiang) - Fix INTx interrupt clearing to avoid missed interrupts (Hou Zhiqiang) * remotes/lorenzo/pci/mobiveil: PCI: mobiveil: Fix INTx interrupt clearing in mobiveil_pcie_isr() PCI: mobiveil: Fix infinite-loop in the INTx handling function PCI: mobiveil: Move PCIe PIO enablement out of inbound window routine PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound window PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound window PCI: mobiveil: Mask out hardcoded bits in inbound/outbound windows setup PCI: mobiveil: Clear the control fields before updating it PCI: mobiveil: Add configured inbound windows counter PCI: mobiveil: Fix the valid check for inbound and outbound windows PCI: mobiveil: Clean-up program_{ib/ob}_windows() PCI: mobiveil: Remove an unnecessary return value check PCI: mobiveil: Fix error return values PCI: mobiveil: Refactor the MEM/IO outbound window initialization PCI: mobiveil: Make some register updates more readable PCI: mobiveil: Reformat the code for readability dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional PCI: mobiveil: Fix devfn check in mobiveil_pcie_valid_device() PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers PCI: mobiveil: Move IRQ chained handler setup out of DT parse PCI: mobiveil: Move the link up waiting out of mobiveil_host_init() PCI: mobiveil: Fix the Class Code field PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window PCI: mobiveil: Update the resource list traversal function PCI: mobiveil: Fix PCI base address in MEM/IO outbound windows PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI PCI: mobiveil: Unify register accessors
| * | PCI: mobiveil: Fix INTx interrupt clearing in mobiveil_pcie_isr()Hou Zhiqiang2019-07-081-3/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current INTx handling function clears all interrupts after handling the first pending; this can potentially cause missing INTx detection. Fix the code to clear only the handled INTx IRQ. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in> Tested-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
| * | PCI: mobiveil: Fix infinite-loop in the INTx handling functionHou Zhiqiang2019-07-081-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the loop handling INTx interrupts in mobiveil_pcie_isr(), there is no code to update the loop control variable, which is causing an infinite loop. Fix the code by reading the interrupt status registers inside the loop. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in> Tested-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
| * | PCI: mobiveil: Move PCIe PIO enablement out of inbound window routineHou Zhiqiang2019-07-081-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the PCIe PIO master enablement to function mobiveil_host_init(). Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| * | PCI: mobiveil: Add upper 32-bit PCI base address setup in inbound windowHou Zhiqiang2019-07-081-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code erroneously sets-up the lower 32-bit PCI base address in the inbound window, which results in inbound transactions not working in 64-bit platforms. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| * | PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound windowHou Zhiqiang2019-07-081-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code erroneously sets-up only the lower 32-bit CPU base address in the outbound window, which results in outbound transactions not working in 64-bit platforms. Fix it. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| * | PCI: mobiveil: Mask out hardcoded bits in inbound/outbound windows setupHou Zhiqiang2019-07-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lower 10 bits of window size field are hardcoded to zero in HW so they can't really be changed but the lower 10-bit of PAB_AXI_AMAP_CTRL register are used for control fields, so while programming inbound and outbout windows decoding we should mask out the lower 10-bit of window size to prevent overriding the control bits. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| * | PCI: mobiveil: Clear the control fields before updating itHou Zhiqiang2019-07-081-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While programming the inbound and outbound windows in program_{ib/ob}_windows() we shoud clear the control fields in the registers before programming it with a new value to prevent stale bits from older configuration. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| * | PCI: mobiveil: Add configured inbound windows counterHou Zhiqiang2019-07-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code only keeps track of the number of outbound windows configured but it does not for inbound windows. Add a counter to keep track of initialized inbound windows. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| * | PCI: mobiveil: Fix the valid check for inbound and outbound windowsHou Zhiqiang2019-07-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In program_ib/ob_windows() check the window index from the function parameter instead of the total number of initialized windows to determine if the specified window is valid. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| * | PCI: mobiveil: Clean-up program_{ib/ob}_windows()Hou Zhiqiang2019-07-081-17/+8Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In function program_ob_windows(), remove the redundant read operations to registers PAB_AXI_AMAP_AXI_WIN and PAB_AXI_AMAP_PEX_WIN_H, and remove the useless definition of 'value'. Rename the parameter 'config_io_bit' to 'type' and then remove the definition of 'type'. In function program_ib_windows(), remove the definitions of 'pio_ctrl_val' and 'amap_ctrl_dw' and reduce to only one variable 'value' to keep the temporary value read from registers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| * | PCI: mobiveil: Remove an unnecessary return value checkHou Zhiqiang2019-07-081-2/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory for the host controller private structure (struct mobiveil_pcie) is allocated together with the pci_host_bridge structure in function devm_pci_alloc_host_bridge(), so it is unnecessary to check the return value when get the private structure pointer. Remove the useless check. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| * | PCI: mobiveil: Fix error return valuesHou Zhiqiang2019-07-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some error return values in the host controller driver are either unconventional or plain wrong. Update them all with the expected return values. Signed-off-by: Hou Zhiqiang <Zhinqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| * | PCI: mobiveil: Refactor the MEM/IO outbound window initializationHou Zhiqiang2019-07-081-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the resource type check into an if/else block and only set-up the outbound window for MEM and IO resource. No functional change intended. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
| * | PCI: mobiveil: Make some register updates more readableHou Zhiqiang2019-07-081-18/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make some register updates more readable use a temporary value to hold the register value and carry out the update. Change the register update sequence to: - Read out the original value from the target register - Update the value - Program the updated value back to the register Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
| * | PCI: mobiveil: Reformat the code for readabilityHou Zhiqiang2019-07-081-101/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | Reformat the code to make it more readable. No functional change intended. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
| * | PCI: mobiveil: Fix devfn check in mobiveil_pcie_valid_device()Hou Zhiqiang2019-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current check for devfn number in mobiveil_pci_valid_device() is wrong in that it flags as invalid functions present in PCI device 0 in the root bus while it is perfectly valid to access all functions in PCI device 0 in the root bus. Update the check in mobiveil_pci_valid_device() to fix the issue. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
| * | PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbersHou Zhiqiang2019-07-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reset value of Primary, Secondary and Subordinate bus numbers is zero which is a broken setup. Program a sensible default value for Primary/Secondary/Subordinate bus numbers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-09 00:19:12 +0200