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| * | target/mips: Only build TCG code when CONFIG_TCG is setPhilippe Mathieu-Daudé2021-01-141-2/+6
| * | target/mips: Extract FPU specific definitions to translate.hPhilippe Mathieu-Daudé2021-01-142-70/+71
| * | target/mips: Declare generic FPU / Coprocessor functions in translate.hPhilippe Mathieu-Daudé2021-01-142-12/+24
| * | target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instructionPhilippe Mathieu-Daudé2021-01-142-362/+368
| * | target/mips: Replace gen_exception_err(err=0) by gen_exception_end()Philippe Mathieu-Daudé2021-01-141-3/+3
| * | target/mips/translate: Add declarations for generic codePhilippe Mathieu-Daudé2021-01-142-38/+57
| * | target/mips/translate: Extract DisasContext structurePhilippe Mathieu-Daudé2021-01-142-37/+51
| * | target/mips: Rename translate_init.c as cpu-defs.cPhilippe Mathieu-Daudé2021-01-142-1/+1
| * | target/mips: Move mmu_init() functions to tlb_helper.cPhilippe Mathieu-Daudé2021-01-143-48/+47Star
| * | target/mips: Fix code style for checkpatch.plPhilippe Mathieu-Daudé2021-01-141-18/+18
| * | target/mips: Rename helper.c as tlb_helper.cPhilippe Mathieu-Daudé2021-01-142-2/+2
| * | target/mips: Move common helpers from helper.c to cpu.cPhilippe Mathieu-Daudé2021-01-143-207/+211
| * | target/mips: Remove consecutive CONFIG_USER_ONLY ifdefsPhilippe Mathieu-Daudé2021-01-141-2/+0Star
| * | target/mips: Add !CONFIG_USER_ONLY comment after #endifPhilippe Mathieu-Daudé2021-01-141-5/+8
| * | target/mips: Extract FPU helpers to 'fpu_helper.h'Philippe Mathieu-Daudé2021-01-1411-50/+69
| * | target/mips: Inline cpu_state_reset() in mips_cpu_reset()Philippe Mathieu-Daudé2021-01-141-17/+9Star
| * | target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6Philippe Mathieu-Daudé2021-01-148-237/+237
| * | target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5Philippe Mathieu-Daudé2021-01-142-3/+3
| * | target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3Philippe Mathieu-Daudé2021-01-141-2/+2
| * | target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2Philippe Mathieu-Daudé2021-01-146-76/+76
| * | target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1Philippe Mathieu-Daudé2021-01-143-30/+30
| * | target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6Philippe Mathieu-Daudé2021-01-145-9/+7Star
| * | target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5Philippe Mathieu-Daudé2021-01-141-2/+1Star
| * | target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3Philippe Mathieu-Daudé2021-01-141-2/+1Star
| * | target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2Philippe Mathieu-Daudé2021-01-143-5/+3Star
| * | target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1Philippe Mathieu-Daudé2021-01-142-7/+6Star
| * | hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()Philippe Mathieu-Daudé2021-01-141-4/+2Star
| * | target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()Philippe Mathieu-Daudé2021-01-142-1/+8
| * | target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1Philippe Mathieu-Daudé2021-01-142-11/+11
| * | target/mips/mips-defs: Reorder CPU_MIPS5 definitionPhilippe Mathieu-Daudé2021-01-141-2/+1Star
| * | target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS commentPhilippe Mathieu-Daudé2021-01-141-6/+0Star
| * | target/mips/addr: Add translation helpers for KSEG1Jiaxun Yang2021-01-142-0/+12
| * | target/mips: Replace CP0_Config0 magic values by proper definitionsPhilippe Mathieu-Daudé2021-01-141-6/+8
| * | target/mips: Add CP0 Config0 register definitions for MIPS3 ISAPhilippe Mathieu-Daudé2021-01-141-1/+9
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* | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210113' into...Peter Maydell2021-01-1421-668/+889
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| * | decodetree: Open files with encoding='utf-8'Philippe Mathieu-Daudé2021-01-131-3/+6
| * | tcg/aarch64: Use tcg_constant_vec with tcg vec expandersRichard Henderson2021-01-131-5/+5
| * | tcg/ppc: Use tcg_constant_vec with tcg vec expandersRichard Henderson2021-01-131-17/+27
| * | tcg: Remove tcg_gen_dup{8,16,32,64}i_vecRichard Henderson2021-01-132-24/+0Star
| * | tcg/i386: Use tcg_constant_vec with tcg vec expandersRichard Henderson2021-01-131-13/+13
| * | tcg: Add tcg_reg_alloc_dup2Richard Henderson2021-01-131-0/+97
| * | tcg: Remove movi and dupi opcodesRichard Henderson2021-01-1313-45/+1Star
| * | tcg/tci: Add special tci_movi_{i32,i64} opcodesRichard Henderson2021-01-133-4/+12
| * | tcg: Use tcg_constant_{i32,i64,vec} with gvec expandersRichard Henderson2021-01-133-77/+59Star
| * | tcg: Use tcg_constant_{i32,i64} with tcg pluginsRichard Henderson2021-01-131-27/+22Star
| * | tcg: Use tcg_constant_{i32,i64} with tcg int expandersRichard Henderson2021-01-132-131/+109Star
| * | tcg: Use tcg_constant_i32 with icount expanderRichard Henderson2021-01-131-12/+13
| * | tcg: Convert tcg_gen_dupi_vec to TCG_CONSTRichard Henderson2021-01-133-40/+15Star
| * | tcg/optimize: Use tcg_constant_internal with constant foldingRichard Henderson2021-01-131-59/+49Star
| * | tcg/optimize: Adjust TempOptInfo allocationRichard Henderson2021-01-131-26/+34
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 14:26:41 +0100