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| * | target/mips: Only build TCG code when CONFIG_TCG is setPhilippe Mathieu-Daudé2021-01-141-2/+6
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-20-f4bug@amsat.org>
| * | target/mips: Extract FPU specific definitions to translate.hPhilippe Mathieu-Daudé2021-01-142-70/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | Extract FPU specific definitions that can be used by ISA / ASE / extensions to translate.h header. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-16-f4bug@amsat.org>
| * | target/mips: Declare generic FPU / Coprocessor functions in translate.hPhilippe Mathieu-Daudé2021-01-142-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some FPU / Coprocessor translation functions / registers can be used by ISA / ASE / extensions out of the big translate.c file. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-15-f4bug@amsat.org>
| * | target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instructionPhilippe Mathieu-Daudé2021-01-142-362/+368
| | | | | | | | | | | | | | | | | | | | | | | | | | | gen_reserved_instruction() is easier to read than generate_exception_end(ctx, EXCP_RI), replace it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-12-f4bug@amsat.org>
| * | target/mips: Replace gen_exception_err(err=0) by gen_exception_end()Philippe Mathieu-Daudé2021-01-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | generate_exception_err(err=0) is simply generate_exception_end(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-11-f4bug@amsat.org>
| * | target/mips/translate: Add declarations for generic codePhilippe Mathieu-Daudé2021-01-142-38/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some CPU translation functions / registers / macros and definitions can be used by ISA / ASE / extensions out of the big translate.c file. Declare them in "translate.h". Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201207235539.4070364-3-f4bug@amsat.org>
| * | target/mips/translate: Extract DisasContext structurePhilippe Mathieu-Daudé2021-01-142-37/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract DisasContext to a new 'translate.h' header so different translation files (ISA, ASE, extensions) can use it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201207235539.4070364-2-f4bug@amsat.org>
| * | target/mips: Rename translate_init.c as cpu-defs.cPhilippe Mathieu-Daudé2021-01-142-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This file is not TCG specific, contains CPU definitions and is consumed by cpu.c. Rename it as such. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-10-f4bug@amsat.org>
| * | target/mips: Move mmu_init() functions to tlb_helper.cPhilippe Mathieu-Daudé2021-01-143-48/+47Star
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-15-f4bug@amsat.org>
| * | target/mips: Fix code style for checkpatch.plPhilippe Mathieu-Daudé2021-01-141-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-14-f4bug@amsat.org>
| * | target/mips: Rename helper.c as tlb_helper.cPhilippe Mathieu-Daudé2021-01-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This file contains functions related to TLB management, rename it as 'tlb_helper.c'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-13-f4bug@amsat.org>
| * | target/mips: Move common helpers from helper.c to cpu.cPhilippe Mathieu-Daudé2021-01-143-207/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rest of helper.c is TLB related. Extract the non TLB specific functions to cpu.c, so we can rename helper.c as tlb_helper.c in the next commit. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-6-f4bug@amsat.org>
| * | target/mips: Remove consecutive CONFIG_USER_ONLY ifdefsPhilippe Mathieu-Daudé2021-01-141-2/+0Star
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-5-f4bug@amsat.org>
| * | target/mips: Add !CONFIG_USER_ONLY comment after #endifPhilippe Mathieu-Daudé2021-01-141-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | To help understand ifdef'ry, add comment after #endif. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-4-f4bug@amsat.org>
| * | target/mips: Extract FPU helpers to 'fpu_helper.h'Philippe Mathieu-Daudé2021-01-1411-50/+69
| | | | | | | | | | | | | | | | | | | | | | | | Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201120210844.2625602-2-f4bug@amsat.org>
| * | target/mips: Inline cpu_state_reset() in mips_cpu_reset()Philippe Mathieu-Daudé2021-01-141-17/+9Star
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-2-f4bug@amsat.org>
| * | target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6Philippe Mathieu-Daudé2021-01-148-237/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
| * | target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5Philippe Mathieu-Daudé2021-01-142-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-15-f4bug@amsat.org>
| * | target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3Philippe Mathieu-Daudé2021-01-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-14-f4bug@amsat.org>
| * | target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2Philippe Mathieu-Daudé2021-01-146-76/+76
| | | | | | | | | | | | | | | | | | | | | | | | The MIPS ISA release 2 is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
| * | target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1Philippe Mathieu-Daudé2021-01-143-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | The MIPS ISA release '1' is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-12-f4bug@amsat.org>
| * | target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6Philippe Mathieu-Daudé2021-01-145-9/+7Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
| * | target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5Philippe Mathieu-Daudé2021-01-141-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-10-f4bug@amsat.org>
| * | target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3Philippe Mathieu-Daudé2021-01-141-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R3 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-9-f4bug@amsat.org>
| * | target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2Philippe Mathieu-Daudé2021-01-143-5/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-8-f4bug@amsat.org>
| * | target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1Philippe Mathieu-Daudé2021-01-142-7/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the single ISA_MIPS32 definition to check if the Release 1 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R1 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-7-f4bug@amsat.org>
| * | hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()Philippe Mathieu-Daudé2021-01-141-4/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Directly check if the CPU supports 64-bit with the recently added cpu_type_is_64bit() helper (inlined). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-6-f4bug@amsat.org>
| * | target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()Philippe Mathieu-Daudé2021-01-142-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS 64-bit ISA is introduced with MIPS3. Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA, and the cpu_type_is_64bit() method to check if a CPU supports this ISA (thus is 64-bit). Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-5-f4bug@amsat.org>
| * | target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1Philippe Mathieu-Daudé2021-01-142-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing the "Release 1" ISA. Rename it with the 'R1' suffix, as the other CPU definitions do. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
| * | target/mips/mips-defs: Reorder CPU_MIPS5 definitionPhilippe Mathieu-Daudé2021-01-141-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move CPU_MIPS5 after CPU_MIPS4 :) Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-3-f4bug@amsat.org>
| * | target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS commentPhilippe Mathieu-Daudé2021-01-141-6/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove a comment added 12 years ago but never used (commit b6d96beda3a: "Use temporary registers for the MIPS FPU emulation"). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-2-f4bug@amsat.org>
| * | target/mips/addr: Add translation helpers for KSEG1Jiaxun Yang2021-01-142-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's useful for bootloader to do I/O operations. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Message-Id: <20201215064507.30148-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
| * | target/mips: Replace CP0_Config0 magic values by proper definitionsPhilippe Mathieu-Daudé2021-01-141-6/+8
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201201132817.2863301-3-f4bug@amsat.org>
| * | target/mips: Add CP0 Config0 register definitions for MIPS3 ISAPhilippe Mathieu-Daudé2021-01-141-1/+9
|/ / | | | | | | | | | | | | | | | | The MIPS3 and MIPS32/64 ISA use different definitions for the CP0 Config0 register. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201201132817.2863301-2-f4bug@amsat.org>
* | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210113' ↵Peter Maydell2021-01-1421-668/+889
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Improvements to tcg constant handling. Force utf8 for decodetree. # gpg: Signature made Thu 14 Jan 2021 02:15:42 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210113: (24 commits) decodetree: Open files with encoding='utf-8' tcg/aarch64: Use tcg_constant_vec with tcg vec expanders tcg/ppc: Use tcg_constant_vec with tcg vec expanders tcg: Remove tcg_gen_dup{8,16,32,64}i_vec tcg/i386: Use tcg_constant_vec with tcg vec expanders tcg: Add tcg_reg_alloc_dup2 tcg: Remove movi and dupi opcodes tcg/tci: Add special tci_movi_{i32,i64} opcodes tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders tcg: Use tcg_constant_{i32,i64} with tcg plugins tcg: Use tcg_constant_{i32,i64} with tcg int expanders tcg: Use tcg_constant_i32 with icount expander tcg: Convert tcg_gen_dupi_vec to TCG_CONST tcg/optimize: Use tcg_constant_internal with constant folding tcg/optimize: Adjust TempOptInfo allocation tcg/optimize: Improve find_better_copy tcg: Introduce TYPE_CONST temporaries tcg: Expand TempOptInfo to 64-bits tcg: Rename struct tcg_temp_info to TempOptInfo tcg: Expand TCGTemp.val to 64-bits ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | decodetree: Open files with encoding='utf-8'Philippe Mathieu-Daudé2021-01-131-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When decodetree.py was added in commit 568ae7efae7, QEMU was using Python 2 which happily reads UTF-8 files in text mode. Python 3 requires either UTF-8 locale or an explicit encoding passed to open(). Now that Python 3 is required, explicit UTF-8 encoding for decodetree source files. To avoid further problems with the user locale, also explicit UTF-8 encoding for the generated C files. Explicit both input/output are plain text by using the 't' mode. This fixes: $ /usr/bin/python3 scripts/decodetree.py test.decode Traceback (most recent call last): File "scripts/decodetree.py", line 1397, in <module> main() File "scripts/decodetree.py", line 1308, in main parse_file(f, toppat) File "scripts/decodetree.py", line 994, in parse_file for line in f: File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode return codecs.ascii_decode(input, self.errors)[0] UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position 80: ordinal not in range(128) Reported-by: Peter Maydell <peter.maydell@linaro.org> Suggested-by: Yonggang Luo <luoyonggang@gmail.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210110000240.761122-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/aarch64: Use tcg_constant_vec with tcg vec expandersRichard Henderson2021-01-131-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to "t1 = -v2, t2 = c - v2". This avoids a serial dependency between t1 and t2. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/ppc: Use tcg_constant_vec with tcg vec expandersRichard Henderson2021-01-131-17/+27
| | | | | | | | | | | | | | | | | | | | | | | | Improve expand_vec_shi to use sign-extraction for MO_32. This allows a single VSPLTISB instruction to load all of the valid shift constants. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Remove tcg_gen_dup{8,16,32,64}i_vecRichard Henderson2021-01-132-24/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | These interfaces have been replaced by tcg_gen_dupi_vec and tcg_constant_vec. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Use tcg_constant_vec with tcg vec expandersRichard Henderson2021-01-131-13/+13
| | | | | | | | | | | | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Add tcg_reg_alloc_dup2Richard Henderson2021-01-131-0/+97
| | | | | | | | | | | | | | | | | | | | | There are several ways we can expand a vector dup of a 64-bit element on a 32-bit host. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Remove movi and dupi opcodesRichard Henderson2021-01-1313-45/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | These are now completely covered by mov from a TYPE_CONST temporary. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/tci: Add special tci_movi_{i32,i64} opcodesRichard Henderson2021-01-133-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | The normal movi opcodes are going away. We need something for TCI to use internally. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Use tcg_constant_{i32,i64,vec} with gvec expandersRichard Henderson2021-01-133-77/+59Star
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Use tcg_constant_{i32,i64} with tcg pluginsRichard Henderson2021-01-131-27/+22Star
| | | | | | | | | | | | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Use tcg_constant_{i32,i64} with tcg int expandersRichard Henderson2021-01-132-131/+109Star
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Use tcg_constant_i32 with icount expanderRichard Henderson2021-01-131-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | We must do this before we adjust tcg_out_movi_i32, lest the under-the-hood poking that we do for icount be broken. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Convert tcg_gen_dupi_vec to TCG_CONSTRichard Henderson2021-01-133-40/+15Star
| | | | | | | | | | | | | | | | | | | | | | | | Because we now store uint64_t in TCGTemp, we can now always store the full 64-bit duplicate immediate. So remove the difference between 32- and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/optimize: Use tcg_constant_internal with constant foldingRichard Henderson2021-01-131-59/+49Star
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/optimize: Adjust TempOptInfo allocationRichard Henderson2021-01-131-26/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not allocate a large block for indexing. Instead, allocate for each temporary as they are seen. In general, this will use less memory, if we consider that most TBs do not touch every target register. This also allows us to allocate TempOptInfo for new temps created during optimization. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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