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* | Merge remote-tracking branch 'remotes/kraxel/tags/ui-20210115-pull-request' ↵Peter Maydell2021-01-156-28/+169
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging ui/gtk: refresh rate fixes. ui/vnc: add support for desktop resize and power contol. ui/vnc: misc bugfixes. # gpg: Signature made Fri 15 Jan 2021 10:24:10 GMT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20210115-pull-request: vnc: add support for extended desktop resize vnc: move initialization to framebuffer_update_request vnc: move check into vnc_cursor_define vnc: Fix a memleak in vnc_display_connect() ui: add support for remote power control to VNC server vnc: fix unfinalized tlscreds for VncDisplay ui/gtk: update monitor interval on egl displays ui/gtk: expose gd_monitor_update_interval ui/gtk: limit virtual console max update interval ui/gtk: rename variable window to widget ui/gtk: don't try to redefine SI prefixes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | vnc: add support for extended desktop resizeGerd Hoffmann2021-01-152-1/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The extended desktop resize encoding adds support for (a) clients sending resize requests to the server, and (b) multihead support. This patch implements (a). All resize requests are rejected by qemu. Qemu can't resize the framebuffer on its own, this is in the hands of the guest, so all qemu can do is forward the request to the guest. Should the guest actually resize the framebuffer we can notify the vnc client later with a separate message. This requires support in the display device. Works with virtio-gpu. https://github.com/rfbproto/rfbproto/blob/master/rfbproto.rst#extendeddesktopsize-pseudo-encoding Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20210112134120.2031837-4-kraxel@redhat.com
| * | vnc: move initialization to framebuffer_update_requestGerd Hoffmann2021-01-151-7/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qemu sends various state info like current cursor shape to newly connected clients in response to a set_encoding message. This is not correct according to the rfb spec. Send that information in response to a full (incremental=0) framebuffer update request instead. Also send the resize information unconditionally, not only in case of an actual server-side change. This makes the qemu vnc server conform to the spec and allows clients to request the complete vnc server state without reconnect. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20210112134120.2031837-3-kraxel@redhat.com
| * | vnc: move check into vnc_cursor_defineGerd Hoffmann2021-01-151-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the check whenever a cursor exists into the vnc_cursor_define() function so callers don't have to do it. Suggested-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20210112134120.2031837-2-kraxel@redhat.com
| * | vnc: Fix a memleak in vnc_display_connect()Alex Chen2021-01-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Free the 'sioc' when the qio_channel_socket_connect_sync() fails. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Alex Chen <alex.chen@huawei.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201126065702.35095-1-alex.chen@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ui: add support for remote power control to VNC serverDaniel P. Berrangé2021-01-153-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "XVP" (Xen VNC Proxy) extension defines a mechanism for a VNC client to issue power control requests to trigger graceful shutdown, reboot, or hard reset. This option is not enabled by default, since we cannot assume that users with VNC access implicitly have administrator access to the guest OS. Thus is it enabled with a boolean "power-control" option e.g. -vnc :1,power-control=on While, QEMU can easily support shutdown and reset, there's no easy way to wire up reboot support at this time. In theory it could be done by issuing a shutdown, followed by a reset, but there's no convenient wiring for such a pairing in QEMU. It also isn't possible to have the VNC server directly talk to QEMU guest agent, since the agent chardev is typically owned by an external mgmt app. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> [ kraxel: rebase to master ] [ kraxel: add missing break ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | vnc: fix unfinalized tlscreds for VncDisplayZihao Chang2021-01-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In vnc_display_open(), if tls-creds is enabled, do object_ref(object ref 1->2) for tls-creds. While in vnc_display_close(), object_unparent sets object ref to 1(2->1) and unparent the object for root. Problem: 1. the object can not be found from the objects_root, while the object is not finalized. 2. the qemu_opts of tls-creds(id: creds0) is not deleted, so new tls object with the same id(creds0) can not be delete & add. Signed-off-by: Zihao Chang <changzihao1@huawei.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20210111131911.805-1-changzihao1@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ui/gtk: update monitor interval on egl displaysNikola Pavlica2021-01-151-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running QEMU's GTK UI without EGL or OGL, the gd_monitor_update_interval function gets executed and the display refresh rate gets updated accordingly. However, when using EGL or just regular OGL, the function never gets executed. Which is why I decided that the function should be in gd_egl_refresh where the display output gets updated, in the same vain as how it's done for normal GTK UIs (aka. those without EGL) - in it's display refresh function. Since the gd_monitor_update_interval function now is exposed, we are going to use it to update the refresh rate. Signed-off-by: Nikola Pavlica <pavlica.nikola@gmail.com> Message-Id: <20210114140153.301473-3-pavlica.nikola@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ui/gtk: expose gd_monitor_update_intervalNikola Pavlica2021-01-152-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gd_egl_refresh function, as the name suggests, is responsible for refreshing displays when using EGL graphics with QEMU's GTK UI. This is a perfect candidate for a function to update the refresh rate in. Since gd_monitor_update_interval is inaccessible from the gd_egl_refresh function, we need to expose/globalize it in the include/ui/gtk.h file. Signed-off-by: Nikola Pavlica <pavlica.nikola@gmail.com> Message-Id: <20210114140153.301473-2-pavlica.nikola@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ui/gtk: limit virtual console max update intervalVolker Rümelin2021-01-151-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Limit the virtual console maximum update interval to GUI_REFRESH_INTERVAL_DEFAULT. This papers over a integer overflow bug in gtk3 on Windows where the reported monitor refresh frequency can be much smaller than the real refresh frequency. The gtk bug report can be found here: https://gitlab.gnome.org/GNOME/gtk/-/issues/3394 On my Windows 10 system gtk reports a monitor refresh rate of 1.511Hz instead of 60.031Hz and slows down the screen update rate in qemu to a crawl. Provided you are affected by the gtk bug on Windows, these are the steps to reproduce the issue: Start qemu with -display gtk and activate all qemu virtual consoles and notice the reduced qemu refresh rate. Activating all virtual consoles is necessary, because gui_update() in ui/console.c uses the minimum of all display change listeners update interval and not yet activated virtual consoles report the default update interval (30ms). Signed-off-by: Volker Rümelin <vr_qemu@t-online.de> Message-Id: <20201213165724.13418-3-vr_qemu@t-online.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ui/gtk: rename variable window to widgetVolker Rümelin2021-01-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The type of the variable window is GtkWidget. Rename the variable from window to widget, because windows and widgets are different things. Signed-off-by: Volker Rümelin <vr_qemu@t-online.de> Message-Id: <20201213165724.13418-2-vr_qemu@t-online.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ui/gtk: don't try to redefine SI prefixesVolker Rümelin2021-01-152-3/+2Star
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Redefining SI prefixes is always wrong. 1s has per definition 1000ms. Remove the misnamed named constant and replace it with a comment explaining the frequency to period conversion in two simple steps. Now you can cancel out the unit mHz in the comment with the implicit unit mHz in refresh_rate_millihz and see why the implicit unit ms for update_interval remains. Signed-off-by: Volker Rümelin <vr_qemu@t-online.de> Message-Id: <20201213165724.13418-1-vr_qemu@t-online.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | Merge remote-tracking branch 'remotes/gkurz-gitlab/tags/9p-next-2021-01-15' ↵Peter Maydell2021-01-151-3/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Fix for CVE-2021-20181 # gpg: Signature made Fri 15 Jan 2021 08:52:19 GMT # gpg: using RSA key B4828BAF943140CEF2A3491071D4D5E5822F73D6 # gpg: Good signature from "Greg Kurz <groug@kaod.org>" [full] # gpg: aka "Gregory Kurz <gregory.kurz@free.fr>" [full] # gpg: aka "[jpeg image of size 3330]" [full] # Primary key fingerprint: B482 8BAF 9431 40CE F2A3 4910 71D4 D5E5 822F 73D6 * remotes/gkurz-gitlab/tags/9p-next-2021-01-15: 9pfs: Fully restart unreclaim loop (CVE-2021-20181) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | 9pfs: Fully restart unreclaim loop (CVE-2021-20181)Greg Kurz2021-01-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Depending on the client activity, the server can be asked to open a huge number of file descriptors and eventually hit RLIMIT_NOFILE. This is currently mitigated using a reclaim logic : the server closes the file descriptors of idle fids, based on the assumption that it will be able to re-open them later. This assumption doesn't hold of course if the client requests the file to be unlinked. In this case, we loop on the entire fid list and mark all related fids as unreclaimable (the reclaim logic will just ignore them) and, of course, we open or re-open their file descriptors if needed since we're about to unlink the file. This is the purpose of v9fs_mark_fids_unreclaim(). Since the actual opening of a file can cause the coroutine to yield, another client request could possibly add a new fid that we may want to mark as non-reclaimable as well. The loop is thus restarted if the re-open request was actually transmitted to the backend. This is achieved by keeping a reference on the first fid (head) before traversing the list. This is wrong in several ways: - a potential clunk request from the client could tear the first fid down and cause the reference to be stale. This leads to a use-after-free error that can be detected with ASAN, using a custom 9p client - fids are added at the head of the list : restarting from the previous head will always miss fids added by a some other potential request All these problems could be avoided if fids were being added at the end of the list. This can be achieved with a QSIMPLEQ, but this is probably too much change for a bug fix. For now let's keep it simple and just restart the loop from the current head. Fixes: CVE-2021-20181 Buglink: https://bugs.launchpad.net/qemu/+bug/1911666 Reported-by: Zero Day Initiative <zdi-disclosures@trendmicro.com> Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-Id: <161064025265.1838153.15185571283519390907.stgit@bahia.lan> Signed-off-by: Greg Kurz <groug@kaod.org>
* | | Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210114' into ↵Peter Maydell2021-01-1533-4433/+4757
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging MIPS patches queue - Simplify CPU/ISA definitions - Various maintenance code movements in translate.c - Convert part of the MSA ASE instructions to decodetree - Convert some instructions removed from Release 6 to decodetree - Remove deprecated 'fulong2e' machine alias # gpg: Signature made Thu 14 Jan 2021 16:16:29 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/mips-20210114: (69 commits) docs/system: Remove deprecated 'fulong2e' machine alias target/mips: Remove vendor specific CPU definitions target/mips: Remove CPU_NANOMIPS32 definition target/mips: Remove CPU_R5900 definition target/mips: Convert Rel6 LL/SC opcodes to decodetree target/mips: Convert Rel6 LLD/SCD opcodes to decodetree target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree target/mips: Convert Rel6 COP1X opcode to decodetree target/mips: Convert Rel6 Special2 opcode to decodetree target/mips: Remove now unreachable LSA/DLSA opcodes code target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes target/mips: Extract LSA/DLSA translation generators target/mips: Use decode_ase_msa() generated from decodetree target/mips: Introduce decode tree bindings for MSA ASE target/mips: Pass TCGCond argument to MSA gen_check_zero_element() target/mips: Extract MSA translation routines ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | docs/system: Remove deprecated 'fulong2e' machine aliasPhilippe Mathieu-Daudé2021-01-143-6/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'fulong2e' machine alias has been marked as deprecated since QEMU v5.1 (commit c3a09ff68dd, the machine is renamed 'fuloong2e'). Time to remove it now. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20210106184602.3771551-1-f4bug@amsat.org>
| * | target/mips: Remove vendor specific CPU definitionsPhilippe Mathieu-Daudé2021-01-142-10/+7Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vendor specific CPU definitions are not very useful. Use the ISA definitions instead, which are more helpful when looking at the various CPU definitions. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210112210152.2072996-4-f4bug@amsat.org>
| * | target/mips: Remove CPU_NANOMIPS32 definitionPhilippe Mathieu-Daudé2021-01-142-5/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already defined as ISA_NANOMIPS32. Remove this incorrect definition and update the single CPU implementing it, the I7200. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210112210152.2072996-3-f4bug@amsat.org>
| * | target/mips: Remove CPU_R5900 definitionPhilippe Mathieu-Daudé2021-01-141-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 823f2897bdd ("target/mips: Disable R5900 support") removed the single CPU using the CPU_R5900 definition. As it is unused, remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210112210152.2072996-2-f4bug@amsat.org>
| * | target/mips: Convert Rel6 LL/SC opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LL/SC opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-14-f4bug@amsat.org>
| * | target/mips: Convert Rel6 LLD/SCD opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LLD/SCD opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-13-f4bug@amsat.org>
| * | target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LDL/LDR/SDL/SDR opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-12-f4bug@amsat.org>
| * | target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-11-f4bug@amsat.org>
| * | target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LWL/LWR/SWL/SWR opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-10-f4bug@amsat.org>
| * | target/mips: Convert Rel6 CACHE/PREF opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CACHE/PREF opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-9-f4bug@amsat.org>
| * | target/mips: Convert Rel6 COP1X opcode to decodetreePhilippe Mathieu-Daudé2021-01-142-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | COP1x opcode has been removed from the Release 6. Add a single decodetree entry for it, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() call. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-8-f4bug@amsat.org>
| * | target/mips: Convert Rel6 Special2 opcode to decodetreePhilippe Mathieu-Daudé2021-01-143-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Special2 opcode have been removed from the Release 6. Add a single decodetree entry for all the opcode class, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() call. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-7-f4bug@amsat.org>
| * | target/mips: Remove now unreachable LSA/DLSA opcodes codePhilippe Mathieu-Daudé2021-01-141-23/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since we switched to decodetree-generated processing, we can remove this now unreachable code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-6-f4bug@amsat.org>
| * | target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodesPhilippe Mathieu-Daudé2021-01-146-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LSA and LDSA opcodes are also available with MIPS release 6. Introduce the decodetree config files and call the decode() helpers in the main decode_opc() loop. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-24-f4bug@amsat.org>
| * | target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodesPhilippe Mathieu-Daudé2021-01-144-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the LSA opcode to the MSA32 decodetree config, add DLSA to a new config for the MSA64 ASE, and call decode_msa64() in the main decode_opc() loop. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-23-f4bug@amsat.org>
| * | target/mips: Extract LSA/DLSA translation generatorsPhilippe Mathieu-Daudé2021-01-144-32/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | Extract gen_lsa() from translate.c and explode it as gen_LSA() and gen_DLSA(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-22-f4bug@amsat.org>
| * | target/mips: Use decode_ase_msa() generated from decodetreePhilippe Mathieu-Daudé2021-01-143-62/+11Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we can decode the MSA ASE with decode_ase_msa(), use it and remove the previous code, now unreachable. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-21-f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
| * | target/mips: Introduce decode tree bindings for MSA ASEPhilippe Mathieu-Daudé2021-01-144-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the 'msa32' decodetree config for the 32-bit MSA ASE. We start by decoding: - the branch instructions, - all instructions based on the MSA opcode. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-20-f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
| * | target/mips: Pass TCGCond argument to MSA gen_check_zero_element()Philippe Mathieu-Daudé2021-01-141-6/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify gen_check_zero_element() by passing the TCGCond argument along. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-25-f4bug@amsat.org>
| * | target/mips: Extract MSA translation routinesPhilippe Mathieu-Daudé2021-01-143-2249/+2266
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract 2200 lines from the huge translate.c to a new file, 'msa_translate.c'. As there are too many inter-dependencies we don't compile it as another object yet, but keep including it in the big translate.o. We gain in code maintainability. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201120210844.2625602-5-f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
| * | target/mips: Declare gen_msa/_branch() in 'translate.h'Philippe Mathieu-Daudé2021-01-142-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make gen_msa() and gen_msa_branch() public declarations so we can keep calling them once extracted from the big translate.c in the next commit. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-18-f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
| * | target/mips: Extract MSA helper definitionsPhilippe Mathieu-Daudé2021-01-142-434/+445
| | | | | | | | | | | | | | | | | | | | | | | | | | | Keep all MSA-related code altogether. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201120210844.2625602-4-f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
| * | target/mips: Extract MSA helpers from op_helper.cPhilippe Mathieu-Daudé2021-01-142-394/+393Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have ~400 lines of MSA helpers in the generic op_helper.c, move them with the other helpers in 'msa_helper.c'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201123204448.3260804-5-f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
| * | target/mips: Move msa_reset() to msa_helper.cPhilippe Mathieu-Daudé2021-01-144-36/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | translate_init.c.inc mostly contains CPU definitions. msa_reset() doesn't belong here, move it with the MSA helpers. One comment style is updated to avoid checkpatch.pl warning. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-15-f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
| * | target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()Philippe Mathieu-Daudé2021-01-141-21/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation of using the decodetree script, explode gen_msa_branch() as following: - OPC_BZ_V -> BxZ_V(EQ) - OPC_BNZ_V -> BxZ_V(NE) - OPC_BZ_[BHWD] -> BxZ(false) - OPC_BNZ_[BHWD] -> BxZ(true) Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-10-f4bug@amsat.org>
| * | target/mips: Remove CPUMIPSState* argument from gen_msa*() methodsPhilippe Mathieu-Daudé2021-01-141-29/+28Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gen_msa*() methods don't use the "CPUMIPSState *env" argument. Remove it to simplify. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-9-f4bug@amsat.org>
| * | target/mips: Extract msa_translate_init() from mips_tcg_init()Philippe Mathieu-Daudé2021-01-142-13/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The msa_wr_d[] registers are only initialized/used by MSA. They are declared static. We want to move them to the new 'msa_translate.c' unit in few commits, without having to declare them global (with extern). Extract first the logic initialization of the MSA registers from the generic initialization. We will later move this function along with the MSA registers to the new C unit. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-8-f4bug@amsat.org>
| * | target/mips: Alias MSA vector registers on FPU scalar registersPhilippe Mathieu-Daudé2021-01-141-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commits 863f264d10f ("add msa_reset(), global msa register") and cb269f273fd ("fix multiple TCG registers covering same data") removed the FPU scalar registers and replaced them by aliases to the MSA vector registers. It is not very clear to have FPU registers displayed with MSA register names, even if MSA ASE is not present. Instead of aliasing FPU registers to the MSA ones (even when MSA is absent), we now alias the MSA ones to the FPU ones (only when MSA is present). Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-7-f4bug@amsat.org>
| * | target/mips: Remove now unused ASE_MSA definitionPhilippe Mathieu-Daudé2021-01-142-5/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't use ASE_MSA anymore (replaced by ase_msa_available() checking MSAP bit from CP0_Config3). Remove it. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-6-f4bug@amsat.org>
| * | target/mips: Simplify MSA TCG logicPhilippe Mathieu-Daudé2021-01-141-12/+11Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only decode MSA opcodes if MSA is present (implemented). Now than check_msa_access() will only be called if MSA is present, the only way to have MIPS_HFLAG_MSA unset is if MSA is disabled (bit CP0C5_MSAEn cleared, see previous commit). Therefore we can remove the 'reserved instruction' exception. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-5-f4bug@amsat.org>
| * | target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSAPhilippe Mathieu-Daudé2021-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MSA presence is expressed by the MSAP bit of CP0_Config3. We don't need to check anything else. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-4-f4bug@amsat.org>
| * | target/mips: Simplify msa_reset()Philippe Mathieu-Daudé2021-01-142-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call msa_reset() unconditionally, but only reset the MSA registers if MSA is implemented. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-3-f4bug@amsat.org>
| * | target/mips: Introduce ase_msa_available() helperPhilippe Mathieu-Daudé2021-01-144-11/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of accessing CP0_Config3 directly and checking the 'MSA Present' bit, introduce an explicit helper, making the code easier to read. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-2-f4bug@amsat.org>
| * | target/mips/translate: Expose check_mips_64() to 32-bit modePhilippe Mathieu-Daudé2021-01-142-7/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow compiling 64-bit specific translation code more generically (and removing #ifdef'ry), allow compiling check_mips_64() on 32-bit targets. If ever called on 32-bit, we obviously emit a reserved instruction exception. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201215225757.764263-3-f4bug@amsat.org>
| * | target/mips/translate: Extract decode_opc_legacy() from decode_opc()Philippe Mathieu-Daudé2021-01-141-20/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we will slowly move to decodetree generated decoders, extract the legacy decoding from decode_opc(), so new decoders are added in decode_opc() while old code is removed from decode_opc_legacy(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-2-f4bug@amsat.org>
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