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* softfloat: Add float64r32 arithmetic routinesRichard Henderson2021-12-171-0/+110
| | | | | | | | | | | | | These variants take a float64 as input, compute the result to infinite precision (as we do with FloatParts), round the result to the precision and dynamic range of float32, and then return the result in the format of float64. This is the operation PowerPC requires for its float32 operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-28-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* softfloat: Add flag specific to signaling nansRichard Henderson2021-12-172-7/+15
| | | | | | | | | PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-8-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* softfloat: Add flag specific to convert non-nan to intRichard Henderson2021-12-171-7/+7
| | | | | | | | | PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-7-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* softfloat: Add flag specific to sqrt(-x)Richard Henderson2021-12-171-1/+1
| | | | | | | | | PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-6-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* softfloat: Add flags specific to Inf / Inf and 0 / 0Richard Henderson2021-12-171-5/+11
| | | | | | | | | PowerPC has these flags, and it's easier to compute them here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-5-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* softfloat: Add flag specific to Inf * 0Richard Henderson2021-12-172-8/+8
| | | | | | | | | PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-4-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* softfloat: Add flag specific to Inf - InfRichard Henderson2021-12-171-1/+2
| | | | | | | | | PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-3-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* softfloat: add APIs to handle alternative sNaN propagation for fmax/fminChih-Min Chao2021-10-292-8/+36
| | | | | | | | | | | | | | | | | | | | | | For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, The original logic: Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan. The alternative path: Set invalid flag if ft1 == sNaN || ft2 == sNaN. Return NaN only if ft1 == NaN && ft2 == NaN. The IEEE 754 spec allows both implementation and some architecture such as riscv choose different defintions in two spec versions. (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to alternative) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211021160847.2748577-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* softfloat: Remove assertion preventing silencing of NaN in default-NaN modePeter Maydell2021-09-011-1/+0Star
| | | | | | | | | | | | | | | | | | | | | In commit a777d6033447a we added an assertion to parts_silence_nan() that prohibits calling float*_silence_nan() when in default-NaN mode. This ties together a property of the output ("do we generate a default NaN when the result is a NaN?") with an operation on an input ("silence this input NaN"). It's true that most of the time when in default-NaN mode you won't need to silence an input NaN, because you can just produce the default NaN as the result instead. But some functions like float*_maxnum() are defined to be able to work with quiet NaNs, so silencing an input SNaN is still reasonable. In particular, the upcoming implementation of MVE VMAXNMV would fall over this assertion if we didn't delete it. Delete the assertion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Use _Generic instead of QEMU_GENERICRichard Henderson2021-06-161-6/+10
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210614233143.1221879-3-richard.henderson@linaro.org>
* softfloat: Fix tp init in float32_exp2Richard Henderson2021-06-141-1/+1
| | | | | | | | | | | Typo in the conversion to FloatParts64. Fixes: 572c4d862ff2 Fixes: Coverity CID 1457457 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210607223812.110596-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* meson: Split out fpu/meson.buildRichard Henderson2021-06-111-0/+1
| | | | | | | Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Use hard-float for {u}int64_to_float{32,64}Richard Henderson2021-06-031-0/+28
| | | | | | | | | | For the normal case of no additional scaling, this reduces the profile contribution of int64_to_float64 to the testcase in the linked issue from 0.81% to 0.04%. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/134 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert modrem operations to FloatPartsRichard Henderson2021-06-033-1243/+295Star
| | | | | | | | Rename to parts$N_modrem. This was the last use of a lot of the legacy infrastructure, so remove it as required. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move floatN_log2 to softfloat-parts.c.incRichard Henderson2021-06-032-99/+152
| | | | | | | | | | | | | | | | | | | | | | Rename to parts$N_log2. Though this is partly a ruse, since I do not believe the code will succeed for float128 without work. Which is ok for now, because we do not need this for more than float32 and float64. Since berkeley-testfloat-3 doesn't support log2, compare float64_log2 vs the system log2. Fix the errors for inputs near 1.0: test: 3ff00000000000b0 +0x1.00000000000b0p+0 sf: 3d2fa00000000000 +0x1.fa00000000000p-45 libm: 3d2fbd422b1bd36f +0x1.fbd422b1bd36fp-45 Error in fraction: 32170028290927 ulp test: 3feec24f6770b100 +0x1.ec24f6770b100p-1 sf: bfad3740d13c9ec0 -0x1.d3740d13c9ec0p-5 libm: bfad3740d13c9e98 -0x1.d3740d13c9e98p-5 Error in fraction: 40 ulp Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert float32_exp2 to FloatPartsRichard Henderson2021-06-031-30/+23Star
| | | | | | | | | Keep the intermediate results in FloatParts instead of converting back and forth between float64. Use muladd instead of separate mul+add. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert floatx80 compare to FloatPartsRichard Henderson2021-06-031-60/+22Star
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert floatx80_scalbn to FloatPartsRichard Henderson2021-06-031-39/+11Star
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert floatx80 to integer to FloatPartsRichard Henderson2021-06-031-294/+42Star
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert floatx80 float conversions to FloatPartsRichard Henderson2021-06-032-384/+67Star
| | | | | | | | This is the last use of commonNaNT and all of the routines that use it, so remove all of them for Werror. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert integer to floatx80 to FloatPartsRichard Henderson2021-06-031-45/+13Star
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert floatx80_round_to_int to FloatPartsRichard Henderson2021-06-031-103/+13Star
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert floatx80_round to FloatPartsRichard Henderson2021-06-031-4/+6
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert floatx80_sqrt to FloatPartsRichard Henderson2021-06-031-71/+11Star
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert floatx80_div to FloatPartsRichard Henderson2021-06-031-87/+13Star
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert floatx80_mul to FloatPartsRichard Henderson2021-06-031-62/+14Star
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert floatx80_add/sub to FloatPartsRichard Henderson2021-06-031-203/+136Star
| | | | | | | | Since this is the first such, this includes all of the packing and unpacking routines as well. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Adjust parts_uncanon_normal for floatx80Richard Henderson2021-06-031-6/+30
| | | | | | | | | | | | | | | | With floatx80_precision_x, the rounding happens across the break between words. Notice this case with frac_lsb = round_mask + 1 -> 0 and check the bits in frac_hi as needed. In addition, since frac_shift == 0, we won't implicitly clear round_mask via the right-shift, so explicitly clear those bits. This fixes rounding for floatx80_precision_[sd]. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Introduce Floatx80RoundPrecRichard Henderson2021-06-031-15/+17
| | | | | | | Use an enumeration instead of raw 32/64/80 values. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Reduce FloatFmtRichard Henderson2021-06-032-20/+15Star
| | | | | | | | | | | Remove frac_lsb, frac_lsbm1, roundeven_mask. Compute these from round_mask in parts$N_uncanon_normal. With floatx80, round_mask will not be tied to frac_shift. Everything else is easily computable. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Split out parts_uncanon_normalRichard Henderson2021-06-032-27/+40
| | | | | | | | We will need to treat the non-normal cases of floatx80 specially, so split out the normal case that we can reuse. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move sqrt_float to softfloat-parts.c.incRichard Henderson2021-06-032-152/+261
| | | | | | | | | | | | | | | | | Rename to parts$N_sqrt. Reimplement float128_sqrt with FloatParts128. Reimplement with the inverse sqrt newton-raphson algorithm from musl. This is significantly faster than even the berkeley sqrt n-r algorithm, because it does not use division instructions, only multiplication. Ordinarily, changing algorithms at the same time as migrating code is a bad idea, but this is the only way I found that didn't break one of the routines at the same time. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move scalbn_decomposed to softfloat-parts.c.incRichard Henderson2021-06-032-69/+55Star
| | | | | | | | Rename to parts$N_scalbn. Reimplement float128_scalbn with FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move compare_floats to softfloat-parts.c.incRichard Henderson2021-06-032-132/+133
| | | | | | | | | Rename to parts$N_compare. Rename all of the intermediate functions to ftype_do_compare. Rename the hard-float functions to ftype_hs_compare. Convert float128 to FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Implement float128_(min|minnum|minnummag|max|maxnum|maxnummag)David Hildenbrand2021-06-031-0/+13
| | | | | | | | | | The float128 implementation is straight-forward. Unfortuantely, we don't have any tests we can simply adjust/unlock. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210517142739.38597-24-david@redhat.com> [rth: Update for changed parts_minmax return value] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move minmax_flags to softfloat-parts.c.incRichard Henderson2021-06-032-130/+156
| | | | | | | | | Rename to parts$N_minmax. Combine 3 bool arguments to a bitmask. Introduce ftype_minmax functions as a common optimization point. Fold bfloat16 expansions into the same macro as the other types. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move uint_to_float to softfloat-parts.c.incRichard Henderson2021-06-032-50/+56
| | | | | | | | | Rename to parts$N_uint_to_float. Reimplement uint64_to_float128 with FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move int_to_float to softfloat-parts.c.incRichard Henderson2021-06-032-98/+70Star
| | | | | | | | | Rename to parts$N_sint_to_float. Reimplement int{32,64}_to_float128 with FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move round_to_uint_and_pack to softfloat-parts.c.incRichard Henderson2021-06-032-278/+147Star
| | | | | | | | Rename to parts$N_float_to_uint. Reimplement float128_to_uint{32,64}{_round_to_zero} with FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfpu: Add float_round_to_odd_infRichard Henderson2021-06-031-2/+4
| | | | | | | | | | | For Arm BFDOT and BFMMLA, we need a version of round-to-odd that overflows to infinity, instead of the max normal number. Cc: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525225817.400336-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* softfloat: Move round_to_int_and_pack to softfloat-parts.c.incRichard Henderson2021-05-162-284/+145Star
| | | | | | | | Rename to parts$N_float_to_sint. Reimplement float128_to_int{32,64}{_round_to_zero} with FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move round_to_int to softfloat-parts.c.incRichard Henderson2021-05-162-327/+262Star
| | | | | | | | | | | | | | At the same time, convert to pointers, split out parts$N_round_to_int_normal, define a macro for parts_round_to_int using QEMU_GENERIC. This necessarily meant some rearrangement to the rount_to_{,u}int_and_pack routines, so go ahead and convert to parts_round_to_int_normal, which in turn allows cleaning up of the raised exception handling. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Convert float-to-float conversions with float128Richard Henderson2021-05-161-134/+69Star
| | | | | | | | Introduce parts_float_to_float_widen and parts_float_to_float_narrow. Use them for float128_to_float{32,64} and float{32,64}_to_float128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Split float_to_floatRichard Henderson2021-05-161-73/+101
| | | | | | | | Split out parts_float_to_ahp and parts_float_to_float. Convert to pointers. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move div_floats to softfloat-parts.c.incRichard Henderson2021-05-162-174/+171Star
| | | | | | | | Rename to parts$N_div. Implement float128_div with FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Introduce sh[lr]_double primitivesRichard Henderson2021-05-161-23/+79
| | | | | | | | Have x86_64 assembly for them, with a fallback. This avoids shuffling values through %cl in the x86 case. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move muladd_floats to softfloat-parts.c.incRichard Henderson2021-05-162-209/+323
| | | | | | | | Rename to parts$N_muladd. Implement float128_muladd with FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move mul_floats to softfloat-parts.c.incRichard Henderson2021-05-162-129/+128Star
| | | | | | | | Rename to parts$N_mul. Reimplement float128_mul with FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Implement float128_add/sub via partsRichard Henderson2021-05-161-221/+36Star
| | | | | | | | Replace the existing Berkeley implementation with the FloatParts implementation. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* softfloat: Move addsub_floats to softfloat-parts.c.incRichard Henderson2021-05-163-141/+255
| | | | | | | | In preparation for implementing multiple sizes. Rename to parts_addsub, split out parts_add/sub_normal for future reuse with muladd. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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