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* fpu/softfloat: re-factor float to float conversionsAlex Bennée2018-05-182-410/+118Star
| | | | | | | | | This allows us to delete a lot of additional boilerplate code which is no longer needed. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: Partial support for ARM Alternative half-precisionAlex Bennée2018-05-181-3/+16
| | | | | | | | | | | | | | For float16 ARM supports an alternative half-precision format which sacrifices the ability to represent NaN/Inf in return for a higher dynamic range. The new FloatFmt flag, arm_althp, is then used to modify the behaviour of canonicalize and round_canonical with respect to representation and exception raising. Usage of this new flag waits until we re-factor float-to-float conversions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: Replace float_class_msnan with parts_silence_nanRichard Henderson2018-05-182-30/+33
| | | | | | | | | | With a canonical representation of NaNs, we can silence an SNaN immediately rather than delay until the final format is known. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: Replace float_class_dnan with parts_default_nanRichard Henderson2018-05-182-27/+48
| | | | | | | | | | | | | | With a canonical representation of NaNs, we can return the default nan directly rather than delay the expansion until the final format is known. Note one case where we uselessly assigned to a.sign, which was overwritten/ignored later when expanding float_class_dnan. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: Introduce parts_is_snan_fracRichard Henderson2018-05-182-10/+17
| | | | | | | Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: Canonicalize NaN fractionRichard Henderson2018-05-181-1/+6
| | | | | | | | | | | Shift the NaN fraction to a canonical position, much like we do for the fraction of normal numbers. This will facilitate manipulation of NaNs within the shared code paths. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: Move softfloat-specialize.h below FloatParts definitionRichard Henderson2018-05-181-10/+10
| | | | | | | | | We want to be able to specialize on the canonical representation. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nanRichard Henderson2018-05-181-56/+118
| | | | | | | | | | The new function assumes that the input is an SNaN and does not double-check. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: Merge NO_SIGNALING_NANS definitionsRichard Henderson2018-05-181-60/+40Star
| | | | | | | | | | Move the ifdef inside the relevant functions instead of duplicating the function declarations. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: Fix conversion from uint64 to float128Petr Tesarik2018-05-181-1/+1
| | | | | | | | | | | | | | | | | The significand is passed to normalizeRoundAndPackFloat128() as high first, low second. The current code passes the integer first, so the result is incorrectly shifted left by 64 bits. This bug affects the emulation of s390x instruction CXLGBR (convert from logical 64-bit binary-integer operand to extended BFP result). Cc: qemu-stable@nongnu.org Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Petr Tesarik <ptesarik@suse.com> Message-Id: <20180511071052.1443-1-ptesarik@suse.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)Peter Maydell2018-05-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | In float-to-integer conversion, if the floating point input converts exactly to the largest or smallest integer that fits in to the result type, this is not an overflow. In this situation we were producing the correct result value, but were incorrectly setting the Invalid flag. For example for Arm A64, "FCVTAS w0, d0" on an input of 0x41dfffffffc00000 should produce 0x7fffffff and set no flags. Fix the boundary case to take the right half of the if() statements. This fixes a regression from 2.11 introduced by the softfloat refactoring. Cc: qemu-stable@nongnu.org Fixes: ab52f973a50 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
* fpu/softfloat: int_to_float ensure r fully initialisedAlex Bennée2018-05-151-1/+1
| | | | | | | | | | Reported by Coverity (CID1390635). We ensure this for uint_to_float later on so we might as well mirror that. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* softfloat: Handle default NaN mode after pickNaNMulAdd, not beforePeter Maydell2018-05-101-20/+28
| | | | | | | | | | | | | | | | | | | | | It is implementation defined whether a multiply-add of (0,inf,qnan) or (inf,0,qnan) raises InvalidaOperation or not, so we let the target-specific pickNaNMulAdd function handle this. This means that we must do the "return the default NaN in default NaN mode" check after the call, not before. Correct the ordering, and restore the comment from the old propagateFloat64MulAddNaN() that warned about this corner case. This fixes a regression from 2.11 for Arm guests where we would incorrectly fail to set the Invalid flag for these cases. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180504100547.14621-1-peter.maydell@linaro.org
* fpu: Bound increment for scalbnRichard Henderson2018-04-171-0/+6
| | | | | | | | | | | | | | | Without bounding the increment, we can overflow exp either here in scalbn_decomposed or when adding the bias in round_canonical. This can result in e.g. underflowing to 0 instead of overflowing to infinity. The old softfloat code did bound the increment. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* fpu/softfloat: check for Inf / x or 0 / x before /0Alex Bennée2018-04-161-5/+5
| | | | | | | | | | | | | | | | | The re-factoring of div_floats changed the order of checking meaning an operation like -inf/0 erroneously raises the divbyzero flag. IEEE-754 (2008) specifies this should only occur for operations on finite operands. We fix this by moving the check on the dividend being Inf/0 to before the divisor is zero check. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180416135442.30606-1-alex.bennee@linaro.org Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* fpu/softfloat: raise float_invalid for NaN/Inf in round_to_int_and_packAlex Bennée2018-04-161-0/+3
| | | | | | | | | | | | | | | | The re-factor broke the raising of INVALID when NaN/Inf is passed to the float_to_int conversion functions. round_to_uint_and_pack got this right for NaN but also missed out the Inf handling. Fixes https://bugs.launchpad.net/qemu/+bug/1759264 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180413140334.26622-3-alex.bennee@linaro.org Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* softfloat: fix {min, max}nummag for same-abs-value inputsEmilio G. Cota2018-04-131-8/+9
| | | | | | | | | | | | | | | | | | Before 8936006 ("fpu/softfloat: re-factor minmax", 2018-02-21), we used to return +Zero for maxnummag(-Zero,+Zero); after that commit, we return -Zero. Fix it by making {min,max}nummag consistent with {min,max}num, deferring to the latter when the absolute value of the operands is the same. With this fix we now pass fp-test. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180413140334.26622-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* fpu: Fix rounding mode for floatN_to_uintM_round_to_zeroRichard Henderson2018-04-101-2/+2
| | | | | | | | | | We incorrectly passed in the current rounding mode instead of float_round_to_zero. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180410055912.934-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* softfloat: fix crash on int conversion of SNaNStef O'Rear2018-03-091-0/+4
| | | | | | Signed-off-by: Stef O'Rear <sorear2@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* RISC-V FPU SupportMichael Clark2018-03-061-3/+4
| | | | | | | | Helper routines for FPU instructions and NaN definitions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
* softfloat: use floatx80_infinity in softfloatLaurent Vivier2018-03-042-14/+39
| | | | | | | | | | | | | | | | Since f3218a8 ("softfloat: add floatx80 constants") floatx80_infinity is defined but never used. This patch updates floatx80 functions to use this definition. This allows to define a different default Infinity value on m68k: the m68k FPU defines infinity with all bits set to zero in the mantissa. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180224201802.911-4-laurent@vivier.eu>
* softfloat: export some functionsLaurent Vivier2018-03-043-924/+11Star
| | | | | | | | | | | | | | | | | | | | Move fpu/softfloat-macros.h to include/fpu/ Export floatx80 functions to be used by target floatx80 specific implementations. Exports: propagateFloatx80NaN(), extractFloatx80Frac(), extractFloatx80Exp(), extractFloatx80Sign(), normalizeFloatx80Subnormal(), packFloatx80(), roundAndPackFloatx80(), normalizeRoundAndPackFloatx80() Also exports packFloat32() that will be used to implement m68k fsinh, fcos, fsin, ftan operations. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180224201802.911-2-laurent@vivier.eu>
* fpu/softfloat: re-factor sqrtAlex Bennée2018-02-211-111/+96Star
| | | | | | | | | | | | | This is a little bit of a departure from softfloat's original approach as we skip the estimate step in favour of a straight iteration. There is a minor optimisation to avoid calculating more bits of precision than we need however this still brings a performance drop, especially for float64 operations. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: re-factor compareAlex Bennée2018-02-211-54/+80
| | | | | | | | The compare function was already expanded from a macro. I keep the macro expansion but move most of the logic into a compare_decomposed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: re-factor minmaxAlex Bennée2018-02-211-107/+120
| | | | | | | | Let's do the same re-factor treatment for minmax functions. I still use the MACRO trick to expand but now all the checking code is common. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: re-factor scalbnAlex Bennée2018-02-211-73/+33Star
| | | | | | | | This is one of the simpler manipulations you could make to a floating point number. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: re-factor int/uint to floatAlex Bennée2018-02-211-159/+163
| | | | | | | | | | These are considerably simpler as the lower order integers can just use the higher order conversion function. As the decomposed fractional part is a full 64 bit rounding and inexact handling comes from the pack functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: re-factor float to int/uintAlex Bennée2018-02-211-755/+180Star
| | | | | | | | | We share the common int64/uint64_pack_decomposed function across all the helpers and simply limit the final result depending on the final size. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: re-factor round_to_intAlex Bennée2018-02-211-174/+145Star
| | | | | | | | | | We can now add float16_round_to_int and use the common round_decomposed and canonicalize functions to have a single implementation for float16/32/64 round_to_int functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* fpu/softfloat: re-factor muladdAlex Bennée2018-02-212-575/+271Star
| | | | | | | | | | We can now add float16_muladd and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 muladd functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* fpu/softfloat: re-factor divAlex Bennée2018-02-212-148/+136Star
| | | | | | | | | | We can now add float16_div and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 versions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* fpu/softfloat: re-factor mulAlex Bennée2018-02-211-128/+81Star
| | | | | | | | | | We can now add float16_mul and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 versions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* fpu/softfloat: re-factor add/subAlex Bennée2018-02-211-427/+465
| | | | | | | | | | We can now add float16_add/sub and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 add and sub functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* fpu/softfloat: define decompose structuresAlex Bennée2018-02-211-1/+85
| | | | | | | | | These structures pave the way for generic softfloat helper routines that will operate on fully decomposed numbers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* fpu/softfloat: move the extract functions to the top of the fileAlex Bennée2018-02-211-66/+54Star
| | | | | | | | | This is pure code-motion during re-factoring as the helpers will be needed earlier. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* fpu/softfloat: improve comments on ARM NaN propagationAlex Bennée2018-02-211-2/+3
| | | | | | | Mention the pseudo-code fragment from which this is based. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* fpu/softfloat: implement float16_squash_input_denormalAlex Bennée2018-02-211-0/+15
| | | | | | | | | This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* softfloat: define floatx80_round()Laurent Vivier2017-06-291-0/+16
| | | | | | | | | | Add a function to round a floatx80 to the defined precision (floatx80_rounding_precision) Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170628204241.32106-5-laurent@vivier.eu>
* softfloat: define 680x0 specific valuesLaurent Vivier2017-06-151-3/+31
| | | | | | Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170611231633.32582-2-laurent@vivier.eu>
* softfloat: Use correct type in float64_to_uint64_round_to_zero()Peter Maydell2017-02-281-1/+1
| | | | | | | | | | | | | In float64_to_uint64_round_to_zero() a typo meant that we were taking the uint64_t return value from float64_to_uint64() and putting it into an int64_t variable before returning it as uint64_t again. Use uint64_t instead of pointlessly casting it back and forth to int64_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* softfloat: Add float128_to_uint32_round_to_zero()Bharata B Rao2017-02-221-0/+28
| | | | | | | | | float128_to_uint32_round_to_zero() is needed by xscvqpuwz instruction of PowerPC ISA 3.0. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* softfloat: Add float128_to_uint64_round_to_zero()Bharata B Rao2017-02-221-0/+59
| | | | | | | | | | | Implement float128_to_uint64() and use that to implement float128_to_uint64_round_to_zero() This is required by xscvqpudz instruction of PowerPC ISA 3.0. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* softfloat: Add round-to-odd rounding modeBharata B Rao2017-02-221-1/+20
| | | | | | | | | | | | | | | | | Power ISA 3.0 introduces a few quadruple precision floating point instructions that support round-to-odd rounding mode. The round-to-odd mode is explained as under: Let Z be the intermediate arithmetic result or the operand of a convert operation. If Z can be represented exactly in the target format, the result is Z. Otherwise the result is either Z1 or Z2 whichever is odd. Here Z1 and Z2 are the next larger and smaller numbers representable in the target format respectively. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* softfloat: Fix the default qNAN for target-ppcBharata B Rao2017-01-311-1/+1
| | | | | | | | | | Currently float128_default_nan() returns 0xFFFF800000000000 in the higher double word, but it should return 0x7FFF800000000000 which is the correct higher double word for default qNAN on PowerPC. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target-hppa: Add softfloat specializationsRichard Henderson2017-01-231-1/+19
| | | | | | | | | | | Like the original MIPS, HPPA has the MSB of an SNaN set. However, it has different rules for silencing an SNaN: (1) msb is cleared and (2) msb-1 must be set if the fraction is now zero, and (implementation defined) may be set always. I haven't checked real hardware but chose the set always alternative because it's easy and within spec. Signed-off-by: Richard Henderson <rth@twiddle.net>
* fpu: add mechanism to check for invalid long double formatsAndrew Dutcher2016-09-151-16/+100
| | | | | | | | | | | | | | | | | | All operations that take a floatx80 as an operand need to have their inputs checked for malformed encodings. In all of these cases, use the function floatx80_invalid_encoding to perform the check. If an invalid operand is found, raise an invalid operation exception, and then return either NaN (for fp-typed results) or the integer indefinite value (the minimum representable signed integer value, for int-typed results). For the non-quiet comparison operations, this touches adjacent code in order to pass style checks. Signed-off-by: Andrew Dutcher <andrew@andrewdutcher.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1471392895-17324-1-git-send-email-andrew@andrewdutcher.com [PMM: changed "1 << 63" to "1ULL << 63" to fix compile errors] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* softfloat: Fix warn about implicit conversion from int to int8_tPranith Kumar2016-08-151-1/+1
| | | | | | | | | Change the flag type to 'uint8_t' to fix the implicit conversion error. Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Message-id: 20160810185502.32015-1-bobby.prani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd()Aleksandar Markovic2016-06-241-12/+29
| | | | | | | | | | | | | | | | | | | Only for Mips platform, and only for cases when snan_bit_is_one is 0, correct the order of argument comparisons in pickNaNMulAdd(). For more info, see [1], page 53, section "3.5.3 NaN Propagation". [1] "MIPS Architecture for Programmers Volume IV-j: The MIPS32 SIMD Architecture Module", Imagination Technologies LTD, Revision 1.12, February 3, 2016 Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [leon.alrae@imgtec.com: * reworded the subject of the patch * swapped if/else code blocks to match the commit description] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* softfloat: For Mips only, correct default NaN valuesAleksandar Markovic2016-06-241-0/+12
| | | | | | | | | | | | | | | | | | | | | | Only for Mips platform, and only for cases when snan_bit_is_one is 0, correct default NaN values (in their 16-, 32-, and 64-bit flavors). For more info, see [1], page 84, Table 6.3 "Value Supplied When a New Quiet NaN Is Created", and [2], page 52, Table 3.7 "Default NaN Encodings". [1] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies LTD, Revision 6.04, November 13, 2015 [2] "MIPS Architecture for Programmers Volume IV-j: The MIPS32 SIMD Architecture Module", Imagination Technologies LTD, Revision 1.12, February 3, 2016 Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* softfloat: Clean code format in fpu/softfloat-specialize.hAleksandar Markovic2016-06-241-29/+28Star
| | | | | | | | | | | | fpu/softfloat-specialize.h is the most critical file in SoftFloat library, since it handles numerous differences between platforms in relation to floating point arithmetics. This patch makes the code in this file more consistent format-wise, and hopefully easier to debug and maintain. Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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