summaryrefslogtreecommitdiffstats
path: root/hw/riscv/sifive_e.c
Commit message (Expand)AuthorAgeFilesLines
* hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI2022-05-241-1/+1
* hw/riscv: Use error_fatal for SoC realisationAlistair Francis2022-01-081-1/+1
* hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+12
* hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-201-4/+7
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-201-1/+1
* hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-201-1/+1
* arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell2021-08-261-1/+0Star
* hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]Bin Meng2021-05-111-1/+1
* Do not include exec/address-spaces.h if it's not really necessaryThomas Huth2021-05-021-1/+0Star
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0Star
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-6/+3Star
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-1/+2
* sifive_e: Register "revb" as class propertyEduardo Habkost2020-09-221-5/+6
* sifive_e: Rename memmap enum constantsEduardo Habkost2020-09-181-41/+41
* hw/riscv: Move sifive_uart model to hw/charBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_e_prci model to hw/miscBin Meng2020-09-101-1/+1
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-1/+2
* target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-101-0/+1
* hw/riscv: Allow creating multiple instances of PLICAnup Patel2020-08-251-1/+1
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-251-1/+1
* hw/riscv: sifive_e: Correct debug block sizeBin Meng2020-07-221-1/+1
* error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster2020-07-101-4/+1Star
* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-101-2/+2
* qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster2020-07-101-2/+1Star
* hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2020-06-191-4/+6
* hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng2020-06-191-12/+12
* sifive_e: Support the revB machineAlistair Francis2020-06-191-4/+30
* qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster2020-06-151-2/+1Star
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster2020-06-151-8/+5Star
* qom: Less verbose object_initialize_child()Markus Armbruster2020-06-151-3/+1Star
* riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster2020-06-151-3/+2Star
* riscv: sifive_e: Manually define the machineAlistair Francis2020-06-031-11/+30
* riscv: sifive_e: Support changing CPU typeCorey Wharton2020-04-291-2/+3
* hw/riscv: Let devices own the MemoryRegion they createPhilippe Mathieu-Daudé2020-03-171-3/+3
* hw/riscv: Use memory_region_init_rom() with read-only regionsPhilippe Mathieu-Daudé2020-03-171-3/+2Star
* hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel2020-02-271-1/+1
* hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)2019-11-251-1/+1
* riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng2019-09-171-15/+8Star
* riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng2019-09-171-2/+2
* Include sysemu/sysemu.h a lot lessMarkus Armbruster2019-08-161-0/+1
* Include hw/hw.h exactly where neededMarkus Armbruster2019-08-161-1/+0Star
* hw/riscv: Replace global smp variables with machine smp propertiesLike Xu2019-07-051-2/+4
* hw/riscv: Split out the boot functionsAlistair Francis2019-06-271-15/+2Star
* RISC-V: Fix a memory leak when realizing a sifive_ePalmer Dabbelt2019-06-241-7/+6Star
* SiFive RISC-V GPIO DeviceFabien Chouteau2019-05-241-2/+26
* riscv: Ensure the kernel start address is correctly castAlistair Francis2019-02-121-1/+1
* elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick2019-02-051-1/+1
* RISC-V: Enable second UART on sifive_e and sifive_uMichael Clark2018-12-201-3/+2Star
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-21 10:55:01 +0100