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* target/arm: factor MDCR_EL2 common handlingRémi Denis-Courmont2021-01-191-16/+22
* target/arm: use arm_hcr_el2_eff() where applicableRémi Denis-Courmont2021-01-191-13/+18
* target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont2021-01-193-29/+16Star
* target/arm: add arm_is_el2_enabled() helperRémi Denis-Courmont2021-01-191-0/+17
* target/arm: remove redundant testsRémi Denis-Courmont2021-01-192-10/+8Star
* target/arm: Use object_property_add_bool for "sve" propertyRichard Henderson2021-01-191-14/+10Star
* target/arm: Add cpu properties to control pauthRichard Henderson2021-01-194-4/+60
* target/arm: Implement an IMPDEF pauth algorithmRichard Henderson2021-01-192-9/+33
* semihosting: Change common-semi API to be architecture-independentKeith Packard2021-01-183-11/+9Star
* semihosting: Move ARM semihosting code to shared directoriesKeith Packard2021-01-182-1123/+0Star
* target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée2021-01-182-47/+30Star
* gdbstub: drop CPUEnv from gdb_exit()Alex Bennée2021-01-181-1/+1
* target/arm: Don't decode insns in the XScale/iWMMXt space as cp insnsPeter Maydell2021-01-121-0/+7
* target/arm: add aarch32 ID register fields to cpu.hLeif Lindholm2021-01-121-0/+28
* target/arm: add aarch64 ID register fields to cpu.hLeif Lindholm2021-01-121-0/+15
* target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.hLeif Lindholm2021-01-121-0/+31
* target/arm: make ARMCPU.ctr 64-bitLeif Lindholm2021-01-121-1/+1
* target/arm: make ARMCPU.clidr 64-bitLeif Lindholm2021-01-121-1/+1
* target/arm: fix typo in cpu.h ID_AA64PFR1 field nameLeif Lindholm2021-01-121-1/+1
* target/arm: enable Small Translation tables in max CPURémi Denis-Courmont2021-01-121-0/+1
* target/arm: ARMv8.4-TTST extensionRémi Denis-Courmont2021-01-122-2/+18
* target/arm: Remove timer_del()/timer_deinit() before timer_free()Peter Maydell2021-01-081-2/+0Star
* target/arm: Implement Cortex-M55 modelPeter Maydell2021-01-081-0/+42
* target/arm: Implement FPCXT_NS fp system registerPeter Maydell2021-01-081-3/+99
* target/arm: Correct store of FPSCR value via FPCXT_SPeter Maydell2021-01-081-6/+6
* target/arm: Fix MTE0_ACTIVERichard Henderson2021-01-081-1/+1
* tcg: Make tb arg to synchronize_from_tb constRichard Henderson2021-01-071-1/+2
* tcg: Make DisasContextBase.tb constRichard Henderson2021-01-071-1/+1
* migration: Replace migration's JSON writer by the general oneMarkus Armbruster2020-12-191-3/+3
* qapi: Use QAPI_LIST_PREPEND() where possibleEric Blake2020-12-192-16/+3Star
* arm/cpu64: Register "aarch64" as class propertyEduardo Habkost2020-12-151-10/+6Star
* arm: do not use ram_size globalPaolo Bonzini2020-12-101-1/+2
* target/arm: Implement M-profile "minimal RAS implementation"Peter Maydell2020-12-102-0/+18
* target/arm: Implement CCR_S.TRD behaviour for SG insnsPeter Maydell2020-12-101-0/+86
* hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bitPeter Maydell2020-12-101-0/+2
* target/arm: Implement new v8.1M VLLDM and VLSTM encodingsPeter Maydell2020-12-102-1/+26
* target/arm: Implement new v8.1M NOCP check for exception returnPeter Maydell2020-12-101-1/+21
* target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failuresPeter Maydell2020-12-101-1/+5
* target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entryPeter Maydell2020-12-101-4/+12
* hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1MPeter Maydell2020-12-102-0/+8
* target/arm: Implement FPCXT_S fp system registerPeter Maydell2020-12-101-0/+58
* target/arm: Factor out preserve-fp-state from full_vfp_access_check()Peter Maydell2020-12-101-18/+27
* target/arm: Use new FPCR_NZCV_MASK constantPeter Maydell2020-12-101-2/+2
* target/arm: Implement M-profile FPSCR_nzcvqcPeter Maydell2020-12-102-0/+40
* target/arm: Implement VLDR/VSTR system registerPeter Maydell2020-12-102-0/+105
* target/arm: Move general-use constant expanders up in translate.cPeter Maydell2020-12-101-21/+25
* target/arm: Refactor M-profile VMSR/VMRS handlingPeter Maydell2020-12-102-11/+168
* target/arm: Enforce M-profile VMRS/VMSR register restrictionsPeter Maydell2020-12-101-1/+4
* target/arm: Implement CLRM instructionPeter Maydell2020-12-102-1/+43
* target/arm: Implement VSCCLRM insnPeter Maydell2020-12-104-11/+111
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