summaryrefslogtreecommitdiffstats
path: root/target/mips
Commit message (Expand)AuthorAgeFilesLines
...
* cpu: move do_unaligned_access to tcg_opsClaudio Fontana2021-02-051-1/+2
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-051-1/+3
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-2/+2
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost2021-02-051-1/+3
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* target/mips: Remove vendor specific CPU definitionsPhilippe Mathieu-Daudé2021-01-142-10/+7Star
* target/mips: Remove CPU_NANOMIPS32 definitionPhilippe Mathieu-Daudé2021-01-142-5/+2Star
* target/mips: Remove CPU_R5900 definitionPhilippe Mathieu-Daudé2021-01-141-1/+0Star
* target/mips: Convert Rel6 LL/SC opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+2
* target/mips: Convert Rel6 LLD/SCD opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+3
* target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+8
* target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+5
* target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+6
* target/mips: Convert Rel6 CACHE/PREF opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+3
* target/mips: Convert Rel6 COP1X opcode to decodetreePhilippe Mathieu-Daudé2021-01-142-1/+2
* target/mips: Convert Rel6 Special2 opcode to decodetreePhilippe Mathieu-Daudé2021-01-143-2/+9
* target/mips: Remove now unreachable LSA/DLSA opcodes codePhilippe Mathieu-Daudé2021-01-141-23/+5Star
* target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodesPhilippe Mathieu-Daudé2021-01-146-0/+80
* target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodesPhilippe Mathieu-Daudé2021-01-144-0/+37
* target/mips: Extract LSA/DLSA translation generatorsPhilippe Mathieu-Daudé2021-01-144-32/+71
* target/mips: Use decode_ase_msa() generated from decodetreePhilippe Mathieu-Daudé2021-01-143-62/+11Star
* target/mips: Introduce decode tree bindings for MSA ASEPhilippe Mathieu-Daudé2021-01-144-0/+68
* target/mips: Pass TCGCond argument to MSA gen_check_zero_element()Philippe Mathieu-Daudé2021-01-141-6/+4Star
* target/mips: Extract MSA translation routinesPhilippe Mathieu-Daudé2021-01-143-2249/+2266
* target/mips: Declare gen_msa/_branch() in 'translate.h'Philippe Mathieu-Daudé2021-01-142-2/+4
* target/mips: Extract MSA helper definitionsPhilippe Mathieu-Daudé2021-01-142-434/+445
* target/mips: Extract MSA helpers from op_helper.cPhilippe Mathieu-Daudé2021-01-142-394/+393Star
* target/mips: Move msa_reset() to msa_helper.cPhilippe Mathieu-Daudé2021-01-144-36/+39
* target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()Philippe Mathieu-Daudé2021-01-141-21/+48
* target/mips: Remove CPUMIPSState* argument from gen_msa*() methodsPhilippe Mathieu-Daudé2021-01-141-29/+28Star
* target/mips: Extract msa_translate_init() from mips_tcg_init()Philippe Mathieu-Daudé2021-01-142-13/+21
* target/mips: Alias MSA vector registers on FPU scalar registersPhilippe Mathieu-Daudé2021-01-141-5/+9
* target/mips: Remove now unused ASE_MSA definitionPhilippe Mathieu-Daudé2021-01-142-5/+4Star
* target/mips: Simplify MSA TCG logicPhilippe Mathieu-Daudé2021-01-141-12/+11Star
* target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSAPhilippe Mathieu-Daudé2021-01-141-1/+1
* target/mips: Simplify msa_reset()Philippe Mathieu-Daudé2021-01-142-4/+5
* target/mips: Introduce ase_msa_available() helperPhilippe Mathieu-Daudé2021-01-144-11/+15
* target/mips/translate: Expose check_mips_64() to 32-bit modePhilippe Mathieu-Daudé2021-01-142-7/+3Star
* target/mips/translate: Extract decode_opc_legacy() from decode_opc()Philippe Mathieu-Daudé2021-01-141-20/+29
* target/mips: Only build TCG code when CONFIG_TCG is setPhilippe Mathieu-Daudé2021-01-141-2/+6
* target/mips: Extract FPU specific definitions to translate.hPhilippe Mathieu-Daudé2021-01-142-70/+71
* target/mips: Declare generic FPU / Coprocessor functions in translate.hPhilippe Mathieu-Daudé2021-01-142-12/+24
* target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instructionPhilippe Mathieu-Daudé2021-01-142-362/+368
* target/mips: Replace gen_exception_err(err=0) by gen_exception_end()Philippe Mathieu-Daudé2021-01-141-3/+3
* target/mips/translate: Add declarations for generic codePhilippe Mathieu-Daudé2021-01-142-38/+57
* target/mips/translate: Extract DisasContext structurePhilippe Mathieu-Daudé2021-01-142-37/+51
* target/mips: Rename translate_init.c as cpu-defs.cPhilippe Mathieu-Daudé2021-01-142-1/+1
* target/mips: Move mmu_init() functions to tlb_helper.cPhilippe Mathieu-Daudé2021-01-143-48/+47Star
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 10:04:55 +0100