| Commit message (Expand) | Author | Age | Files | Lines |
... | |
* | target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -4/+5 |
* | target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -4/+6 |
* | target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -2/+3 |
* | target/mips: Convert Rel6 COP1X opcode to decodetree | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -1/+2 |
* | target/mips: Convert Rel6 Special2 opcode to decodetree | Philippe Mathieu-Daudé | 2021-01-14 | 3 | -2/+9 |
* | target/mips: Remove now unreachable LSA/DLSA opcodes code | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -23/+5 |
* | target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes | Philippe Mathieu-Daudé | 2021-01-14 | 6 | -0/+80 |
* | target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes | Philippe Mathieu-Daudé | 2021-01-14 | 4 | -0/+37 |
* | target/mips: Extract LSA/DLSA translation generators | Philippe Mathieu-Daudé | 2021-01-14 | 4 | -32/+71 |
* | target/mips: Use decode_ase_msa() generated from decodetree | Philippe Mathieu-Daudé | 2021-01-14 | 3 | -62/+11 |
* | target/mips: Introduce decode tree bindings for MSA ASE | Philippe Mathieu-Daudé | 2021-01-14 | 4 | -0/+68 |
* | target/mips: Pass TCGCond argument to MSA gen_check_zero_element() | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -6/+4 |
* | target/mips: Extract MSA translation routines | Philippe Mathieu-Daudé | 2021-01-14 | 3 | -2249/+2266 |
* | target/mips: Declare gen_msa/_branch() in 'translate.h' | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -2/+4 |
* | target/mips: Extract MSA helper definitions | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -434/+445 |
* | target/mips: Extract MSA helpers from op_helper.c | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -394/+393 |
* | target/mips: Move msa_reset() to msa_helper.c | Philippe Mathieu-Daudé | 2021-01-14 | 4 | -36/+39 |
* | target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -21/+48 |
* | target/mips: Remove CPUMIPSState* argument from gen_msa*() methods | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -29/+28 |
* | target/mips: Extract msa_translate_init() from mips_tcg_init() | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -13/+21 |
* | target/mips: Alias MSA vector registers on FPU scalar registers | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -5/+9 |
* | target/mips: Remove now unused ASE_MSA definition | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -5/+4 |
* | target/mips: Simplify MSA TCG logic | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -12/+11 |
* | target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -1/+1 |
* | target/mips: Simplify msa_reset() | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -4/+5 |
* | target/mips: Introduce ase_msa_available() helper | Philippe Mathieu-Daudé | 2021-01-14 | 4 | -11/+15 |
* | target/mips/translate: Expose check_mips_64() to 32-bit mode | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -7/+3 |
* | target/mips/translate: Extract decode_opc_legacy() from decode_opc() | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -20/+29 |
* | target/mips: Only build TCG code when CONFIG_TCG is set | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -2/+6 |
* | target/mips: Extract FPU specific definitions to translate.h | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -70/+71 |
* | target/mips: Declare generic FPU / Coprocessor functions in translate.h | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -12/+24 |
* | target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -362/+368 |
* | target/mips: Replace gen_exception_err(err=0) by gen_exception_end() | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -3/+3 |
* | target/mips/translate: Add declarations for generic code | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -38/+57 |
* | target/mips/translate: Extract DisasContext structure | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -37/+51 |
* | target/mips: Rename translate_init.c as cpu-defs.c | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -1/+1 |
* | target/mips: Move mmu_init() functions to tlb_helper.c | Philippe Mathieu-Daudé | 2021-01-14 | 3 | -48/+47 |
* | target/mips: Fix code style for checkpatch.pl | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -18/+18 |
* | target/mips: Rename helper.c as tlb_helper.c | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -2/+2 |
* | target/mips: Move common helpers from helper.c to cpu.c | Philippe Mathieu-Daudé | 2021-01-14 | 3 | -207/+211 |
* | target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -2/+0 |
* | target/mips: Add !CONFIG_USER_ONLY comment after #endif | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -5/+8 |
* | target/mips: Extract FPU helpers to 'fpu_helper.h' | Philippe Mathieu-Daudé | 2021-01-14 | 10 | -50/+68 |
* | target/mips: Inline cpu_state_reset() in mips_cpu_reset() | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -17/+9 |
* | target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 | Philippe Mathieu-Daudé | 2021-01-14 | 7 | -236/+236 |
* | target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -3/+3 |
* | target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -2/+2 |
* | target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 | Philippe Mathieu-Daudé | 2021-01-14 | 5 | -75/+75 |
* | target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 | Philippe Mathieu-Daudé | 2021-01-14 | 3 | -30/+30 |
* | target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 | Philippe Mathieu-Daudé | 2021-01-14 | 4 | -7/+6 |