| Commit message (Expand) | Author | Age | Files | Lines |
* | target/mips: Rename decode_opc_mxu() as decode_ase_mxu() | Philippe Mathieu-Daudé | 2021-03-13 | 1 | -2/+2 |
* | target/mips: Move MUL opcode check from decode_mxu() to decode_legacy() | Philippe Mathieu-Daudé | 2021-03-13 | 1 | -14/+5 |
* | target/mips: Use OPC_MUL instead of OPC__MXU_MUL | Philippe Mathieu-Daudé | 2021-03-13 | 1 | -2/+1 |
* | target/mips: Pass instruction opcode to decode_opc_mxu() | Philippe Mathieu-Daudé | 2021-03-13 | 1 | -7/+7 |
* | target/mips: Remove unused CPUMIPSState* from MXU functions | Philippe Mathieu-Daudé | 2021-03-13 | 1 | -10/+10 |
* | target/mips: Remove XBurst Media eXtension Unit dead code | Philippe Mathieu-Daudé | 2021-03-13 | 1 | -1286/+0 |
* | target/mips: Rewrite complex ifdef'ry | Philippe Mathieu-Daudé | 2021-03-13 | 1 | -4/+7 |
* | target/mips/meson: Restrict mips-semi.c to TCG | Philippe Mathieu-Daudé | 2021-03-13 | 1 | -1/+1 |
* | target/mips/meson: Introduce mips_tcg source set | Philippe Mathieu-Daudé | 2021-03-13 | 1 | -2/+5 |
* | Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul... | Peter Maydell | 2021-03-11 | 1 | -2/+2 |
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| * | sysemu: Let VMChangeStateHandler take boolean 'running' argument | Philippe Mathieu-Daudé | 2021-03-09 | 1 | -2/+2 |
* | | Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-docs-xen-upda... | Peter Maydell | 2021-03-11 | 3 | -4/+4 |
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| * | | semihosting: Move include/hw/semihosting/ -> include/semihosting/ | Philippe Mathieu-Daudé | 2021-03-10 | 3 | -4/+4 |
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* / | clock: Add ClockEvent parameter to callbacks | Peter Maydell | 2021-03-08 | 1 | -1/+1 |
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* | target/mips: Use GPR move functions in gen_HILO1_tx79() | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -17/+4 |
* | target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers | Philippe Mathieu-Daudé | 2021-02-21 | 2 | -0/+22 |
* | target/mips: Rename 128-bit upper halve GPR registers | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -1/+3 |
* | target/mips: Promote 128-bit multimedia registers as global ones | Philippe Mathieu-Daudé | 2021-02-21 | 3 | -27/+34 |
* | target/mips: Make cpu_HI/LO registers public | Philippe Mathieu-Daudé | 2021-02-21 | 2 | -1/+2 |
* | target/mips: Include missing "tcg/tcg.h" header | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -0/+1 |
* | target/mips: Remove unused 'rw' argument from page_table_walk_refill() | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -3/+3 |
* | target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType | Philippe Mathieu-Daudé | 2021-02-21 | 2 | -10/+10 |
* | target/mips: Let get_seg*_physical_address() take MMUAccessType arg | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -5/+6 |
* | target/mips: Let get_physical_address() take MMUAccessType argument | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -10/+10 |
* | target/mips: Let raise_mmu_exception() take MMUAccessType argument | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -5/+5 |
* | target/mips: Let cpu_mips_translate_address() take MMUAccessType arg | Philippe Mathieu-Daudé | 2021-02-21 | 2 | -4/+4 |
* | target/mips: Let do_translate_address() take MMUAccessType argument | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -3/+4 |
* | target/mips: Replace magic value by MMU_DATA_LOAD definition | Philippe Mathieu-Daudé | 2021-02-21 | 2 | -2/+2 |
* | target/mips: Remove unused MMU definitions | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -16/+0 |
* | target/mips: Remove access_type argument from get_physical_address() | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -13/+9 |
* | target/mips: Remove access_type arg from get_segctl_physical_address() | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -10/+10 |
* | target/mips: Remove access_type argument from get_seg_physical_address | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -3/+3 |
* | target/mips: Remove access_type argument from map_address() handler | Philippe Mathieu-Daudé | 2021-02-21 | 2 | -12/+11 |
* | target/mips: fetch code with translator_ld | Philippe Mathieu-Daudé | 2021-02-21 | 1 | -10/+10 |
* | target/mips: Create mips_io_recompile_replay_branch | Richard Henderson | 2021-02-18 | 1 | -0/+18 |
* | sev/i386: Don't allow a system reset under an SEV-ES guest | Tom Lendacky | 2021-02-16 | 1 | -0/+5 |
* | cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass | Claudio Fontana | 2021-02-05 | 1 | -13/+23 |
* | cpu: move do_unaligned_access to tcg_ops | Claudio Fontana | 2021-02-05 | 1 | -1/+2 |
* | cpu: move cc->transaction_failed to tcg_ops | Claudio Fontana | 2021-02-05 | 1 | -1/+3 |
* | cpu: move cc->do_interrupt to tcg_ops | Claudio Fontana | 2021-02-05 | 1 | -2/+2 |
* | cpu: Move tlb_fill to tcg_ops | Eduardo Habkost | 2021-02-05 | 1 | -1/+1 |
* | cpu: Move cpu_exec_* to tcg_ops | Eduardo Habkost | 2021-02-05 | 1 | -1/+1 |
* | cpu: Move synchronize_from_tb() to tcg_ops | Eduardo Habkost | 2021-02-05 | 1 | -1/+3 |
* | cpu: Introduce TCGCpuOperations struct | Eduardo Habkost | 2021-02-05 | 1 | -1/+1 |
* | target/mips: Remove vendor specific CPU definitions | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -10/+7 |
* | target/mips: Remove CPU_NANOMIPS32 definition | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -5/+2 |
* | target/mips: Remove CPU_R5900 definition | Philippe Mathieu-Daudé | 2021-01-14 | 1 | -1/+0 |
* | target/mips: Convert Rel6 LL/SC opcodes to decodetree | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -2/+2 |
* | target/mips: Convert Rel6 LLD/SCD opcodes to decodetree | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -2/+3 |
* | target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree | Philippe Mathieu-Daudé | 2021-01-14 | 2 | -4/+8 |