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path: root/target/riscv/cpu.h
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* target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich2022-02-161-0/+3
* target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC...Philipp Tomsich2022-02-161-37/+41
* target/riscv: Remove VILL field in VTYPELIU Zhiwei2022-01-211-1/+0Star
* target/riscv: Adjust vsetvl according to XLENLIU Zhiwei2022-01-211-0/+5
* target/riscv: Split out the vill from vtypeLIU Zhiwei2022-01-211-0/+1
* target/riscv: Split pm_enabled into mask and baseLIU Zhiwei2022-01-211-1/+2
* target/riscv: Create current pm fields in envLIU Zhiwei2022-01-211-0/+4
* target/riscv: Create xl field in envLIU Zhiwei2022-01-211-0/+31
* target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang2022-01-211-0/+1
* target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang2022-01-211-0/+1
* target/riscv: Add kvm_riscv_get/put_regs_timerYifei Jiang2022-01-211-0/+7
* target/riscv: Add host cpu typeYifei Jiang2022-01-211-0/+1
* target/riscv: Support start kernel directly by KVMYifei Jiang2022-01-211-0/+3
* target/riscv: Implement the stval/mtval illegal instructionAlistair Francis2022-01-081-0/+2
* target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot2022-01-081-0/+7
* target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot2022-01-081-0/+5
* target/riscv: adding high part of some csrsFrédéric Pétrot2022-01-081-0/+4
* target/riscv: support for 128-bit M extensionFrédéric Pétrot2022-01-081-0/+3
* target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot2022-01-081-0/+1
* target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot2022-01-081-0/+2
* target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang2021-12-201-0/+1
* target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang2021-12-201-9/+18
* target/riscv: rvv-1.0: add VMA and VTAFrank Chang2021-12-201-0/+2
* target/riscv: rvv-1.0: add fractional LMULFrank Chang2021-12-201-12/+14
* target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang2021-12-201-2/+3
* target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei2021-12-201-0/+2
* target/riscv: drop vector 0.7.1 and add 1.0 supportFrank Chang2021-12-201-1/+1
* target/riscv: zfh: implement zfhmin extensionFrank Chang2021-12-201-0/+1
* target/riscv: zfh: half-precision load and storeKito Cheng2021-12-201-0/+1
* target/riscv: remove force HS exceptionJose Martins2021-10-291-2/+0Star
* target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev2021-10-281-0/+2
* target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo2021-10-281-0/+11
* target/riscv: Add J-extension into RISC-VAlexey Baturo2021-10-281-0/+2
* target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson2021-10-211-0/+2
* target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-211-1/+8
* target/riscv: Split misa.mxl and misa.extRichard Henderson2021-10-211-7/+8
* target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson2021-10-211-45/+2Star
* target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang2021-10-211-7/+7
* target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang2021-10-071-0/+4
* target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich2021-10-071-3/+0Star
* target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich2021-10-071-0/+4
* hw/core: Make do_unaligned_access noreturnRichard Henderson2021-09-221-1/+1
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-221-2/+0Star
* target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-141-1/+1
* target/riscv: rvb: add b-ext version cpu optionFrank Chang2021-06-081-0/+3
* target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2021-06-081-0/+1
* target/riscv: rvb: count leading/trailing zerosKito Cheng2021-06-081-0/+1
* target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2021-06-081-2/+0Star
* target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé2021-06-081-0/+2
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