summaryrefslogtreecommitdiffstats
path: root/target/riscv/csr.c
Commit message (Expand)AuthorAgeFilesLines
* target/riscv: Relax UXL field for debuggingLIU Zhiwei2022-01-211-4/+4
* target/riscv: Enable uxl field writeLIU Zhiwei2022-01-211-6/+22
* target/riscv: Split out the vill from vtypeLIU Zhiwei2022-01-211-1/+12
* target/riscv: Create current pm fields in envLIU Zhiwei2022-01-211-0/+19
* target/riscv: Relax debug check for pm writeLIU Zhiwei2022-01-211-0/+3
* target/riscv: Create xl field in envLIU Zhiwei2022-01-211-0/+2
* target/riscv: Adjust pmpcfg access with mxlLIU Zhiwei2022-01-211-0/+19
* target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang2022-01-211-1/+1
* target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang2022-01-211-1/+5
* target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot2022-01-081-30/+165
* target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot2022-01-081-0/+17
* target/riscv: rvv-1.0: implement vstart CSRFrank Chang2021-12-201-1/+5
* target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registersFrank Chang2021-12-201-0/+5
* target/riscv: rvv-1.0: add vlenb registerGreentime Hu2021-12-201-0/+7
* target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei2021-12-201-0/+17
* target/riscv: rvv-1.0: remove rvv related codes from fcsr registersFrank Chang2021-12-201-13/+0Star
* target/riscv: rvv-1.0: introduce writable misa.v fieldFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei2021-12-201-1/+1
* target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirtyFrank Chang2021-12-201-0/+1
* target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei2021-12-201-1/+11
* target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo2021-10-281-0/+285
* target/riscv: Compute mstatus.sd on demandRichard Henderson2021-10-221-15/+22
* target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson2021-10-211-0/+3
* target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-211-12/+12
* target/riscv: Split misa.mxl and misa.extRichard Henderson2021-10-211-15/+29
* target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng2021-09-211-12/+12
* target/riscv: Fix satp writeLIU Zhiwei2021-09-201-1/+1
* target/riscv: Fix hgeie, hgeipRichard Henderson2021-09-011-18/+8Star
* target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson2021-09-011-8/+15
* target/riscv: Add User CSRs read-only checkLIU Zhiwei2021-09-011-3/+5
* target/riscv: Correct a comment in riscv_csrrw()Bin Meng2021-09-011-1/+1
* target/riscv: hardwire bits in hideleg and hedelegJose Martins2021-07-151-23/+31
* target/riscv: csr: Remove redundant check in fp csr read/write routinesBin Meng2021-07-151-24/+0Star
* target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis2021-05-111-4/+15
* target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis2021-05-111-2/+10
* target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis2021-05-111-1/+8
* target/riscv: Add ePMP CSR access functionsHou Weiying2021-05-111-0/+24
* target/riscv: Use RISCVException enum for CSR accessAlistair Francis2021-05-111-19/+18Star
* target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis2021-05-111-255/+374
* target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis2021-05-111-1/+5
* target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis2021-05-111-36/+44
* target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-111-32/+10Star
* target/riscv: Fix read and write accesses to vsip and vsieGeorg Kotheimer2021-03-231-34/+34
* target/riscv: Make VSTIP and VSEIP read-only in hipGeorg Kotheimer2021-03-231-3/+4
* target/riscv: fix vs() to return proper error codeFrank Chang2021-03-231-1/+1
* target/riscv: Add CSR name in the CSR function tableBin Meng2021-01-161-84/+248
* target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng2021-01-161-9/+1Star
* target/riscv: csr: Remove compile time XLEN checksAlistair Francis2020-12-181-85/+91
* target/riscv/csr.c : add space before the open parenthesis '('Xinhao Zhang2020-11-031-1/+1
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-031-8/+10
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 02:59:01 +0100