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path: root/target/riscv/insn_trans
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* target/riscv: Split gen_arith_imm into functional and tempRichard Henderson2019-05-241-7/+7
* target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson2019-05-241-115/+0Star
* target/riscv: Use pattern groups in insn16.decodeRichard Henderson2019-05-242-63/+6Star
* target/riscv: Merge argument decode for RVC shiftiRichard Henderson2019-05-241-47/+0Star
* target/riscv: Merge argument sets for insn32 and insn16Richard Henderson2019-05-241-133/+11Star
* RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau2019-05-242-7/+7
* decodetree: Add DisasContext argument to !function expandersRichard Henderson2019-05-061-5/+5
* target/riscv: Fix wrong expanding for c.fswspKito Cheng2019-03-261-1/+1
* target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt2019-03-221-2/+2
* target/riscv: Fix manually parsed 16 bit insnBastian Koppelmann2019-03-181-5/+25
* target/riscv: Rename trans_arith to gen_arithBastian Koppelmann2019-03-132-16/+16
* target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann2019-03-131-24/+31
* target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann2019-03-131-30/+63
* target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann2019-03-131-14/+7Star
* target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann2019-03-131-19/+79
* target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann2019-03-131-8/+19
* target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann2019-03-131-14/+21
* target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann2019-03-131-13/+33
* target/riscv: Remove gen_jalr()Bastian Koppelmann2019-03-131-1/+27
* target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann2019-03-131-0/+101
* target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann2019-03-131-0/+151
* target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann2019-03-131-0/+75
* target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann2019-03-131-0/+110
* target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann2019-03-131-0/+82
* target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann2019-03-131-0/+360
* target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann2019-03-131-0/+60
* target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann2019-03-131-0/+379
* target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann2019-03-131-0/+58
* target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann2019-03-131-0/+160
* target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann2019-03-131-0/+113
* target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann2019-03-131-0/+79
* target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann2019-03-131-0/+19
* target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann2019-03-131-0/+168
* target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann2019-03-131-0/+20
* target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann2019-03-131-0/+48
* target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann2019-03-131-0/+49
* target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann2019-03-131-0/+35
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