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path: root/target/riscv/translate.c
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* target/riscv: Split gen_arith_imm into functional and tempRichard Henderson2019-05-241-2/+17
* target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson2019-05-241-1/+0Star
* target/riscv: Merge argument decode for RVC shiftiRichard Henderson2019-05-241-0/+6
* target/riscv: Use --static-decode for decodetreeRichard Henderson2019-05-241-3/+0Star
* target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson2019-05-241-0/+18
* RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau2019-05-241-5/+25
* decodetree: Add DisasContext argument to !function expandersRichard Henderson2019-05-061-2/+2
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt2019-03-221-0/+21
* target/riscv: Remove decode_RV32_64G()Bastian Koppelmann2019-03-131-20/+1Star
* target/riscv: Remove gen_system()Bastian Koppelmann2019-03-131-34/+0Star
* target/riscv: Rename trans_arith to gen_arithBastian Koppelmann2019-03-131-2/+2
* target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann2019-03-131-187/+133Star
* target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann2019-03-131-41/+18Star
* target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann2019-03-131-15/+25
* target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann2019-03-131-80/+27Star
* target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann2019-03-131-3/+5
* target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann2019-03-131-2/+4
* target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann2019-03-131-47/+0Star
* target/riscv: Remove gen_jalr()Bastian Koppelmann2019-03-131-38/+0Star
* target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann2019-03-131-81/+2Star
* target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann2019-03-131-117/+1Star
* target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann2019-03-131-37/+16Star
* target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann2019-03-131-56/+1Star
* target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann2019-03-131-600/+1Star
* target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann2019-03-131-0/+1
* target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann2019-03-131-0/+1
* target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann2019-03-131-144/+0Star
* target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann2019-03-131-0/+1
* target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann2019-03-131-9/+7Star
* target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann2019-03-131-42/+1Star
* target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann2019-03-131-12/+0Star
* target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann2019-03-131-9/+0Star
* target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann2019-03-131-7/+0Star
* target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann2019-03-131-11/+1Star
* target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann2019-03-131-14/+17
* RISC-V: Add misa.MAFD checks to translateMichael Clark2019-02-121-0/+158
* RISC-V: Add misa to DisasContextMichael Clark2019-02-121-35/+40
* RISC-V: Add priv_ver to DisasContextAlistair Francis2019-02-121-2/+5
* RISC-V: Mark mstatus.fs dirtyRichard Henderson2019-02-121-1/+39
* RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson2019-02-121-5/+5
* RISC-V: Respect fences for user-only emulatorsPalmer Dabbelt2018-11-141-2/+0Star
* target/riscv: Fix sfence.vm/a both available in any priv versionBastian Koppelmann2018-11-141-5/+13
* target/riscv: Fix FCLASS_D being treated as RV64 onlyBastian Koppelmann2018-11-141-1/+3
* target/riscv: call gen_goto_tb on DISAS_TOO_MANYEmilio G. Cota2018-09-051-6/+1Star
* target/riscv: optimize indirect branchesEmilio G. Cota2018-09-051-1/+1
* target/riscv: optimize cross-page direct jumps in softmmuEmilio G. Cota2018-09-051-1/+1
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-10/+10
* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...Peter Maydell2018-05-111-49/+17Star
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| * target/riscv: Use new atomic min/max expandersRichard Henderson2018-05-101-49/+17Star
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