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* hw/core: Constify TCGCPUOpsRichard Henderson2021-05-271-1/+1
* cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Move CPUClass::write_elf* to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-2/+2
* cpu: Move CPUClass::vmsd to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé2021-05-271-0/+8
* cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé2021-05-271-2/+1Star
* target/riscv: Fix the RV64H decode commentAlistair Francis2021-05-111-1/+1
* target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis2021-05-115-72/+39Star
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-1114-150/+166
* target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis2021-05-111-6/+0Star
* target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis2021-05-111-6/+0Star
* target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis2021-05-114-28/+56
* target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis2021-05-113-14/+27
* target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis2021-05-112-20/+15Star
* target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis2021-05-112-7/+8
* target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis2021-05-112-7/+5Star
* target/riscv: fix a typo with interrupt namesEmmanuel Blot2021-05-111-1/+1
* target/riscv: fix exception index on instruction access faultEmmanuel Blot2021-05-111-1/+3
* target/riscv: fix vrgather macro index variable type bugFrank Chang2021-05-111-2/+4
* target/riscv: Add ePMP support for the Ibex CPUAlistair Francis2021-05-111-0/+1
* target/riscv/pmp: Remove outdated commentAlistair Francis2021-05-111-4/+0Star
* target/riscv: Add a config option for ePMPHou Weiying2021-05-112-0/+11
* target/riscv: Implementation of enhanced PMP (ePMP)Hou Weiying2021-05-111-8/+146
* target/riscv: Add ePMP CSR access functionsHou Weiying2021-05-115-0/+76
* target/riscv: Add the ePMP featureAlistair Francis2021-05-111-0/+1
* target/riscv: Define ePMP mseccfgHou Weiying2021-05-111-0/+3
* target/riscv: Fix the PMP is locked check when using TORAlistair Francis2021-05-111-10/+16
* target/riscv: Fixup saturate subtract functionLIU Zhiwei2021-05-111-4/+4
* riscv: don't look at SUM when accessing memory from a debugger contextJade Fink2021-05-111-8/+12
* target/riscv: Use RISCVException enum for CSR accessAlistair Francis2021-05-114-36/+38
* target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis2021-05-112-261/+382
* target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis2021-05-111-1/+5
* target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis2021-05-112-37/+46
* target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis2021-05-113-24/+26
* target/riscv: Add Shakti C class CPUVijai Kumar K2021-05-112-0/+2
* target/riscv: Align the data type of reset vector addressDylan Jhong2021-05-111-1/+1
* target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-117-72/+23Star
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0Star
* target/riscv: Prevent lost illegal instruction exceptionsGeorg Kotheimer2021-03-231-178/+1Star
* target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer2021-03-233-13/+13
* target/riscv: Fix read and write accesses to vsip and vsieGeorg Kotheimer2021-03-231-34/+34
* target/riscv: Use background registers also for MSTATUS_MPVGeorg Kotheimer2021-03-231-1/+1
* target/riscv: Make VSTIP and VSEIP read-only in hipGeorg Kotheimer2021-03-231-3/+4
* target/riscv: Adjust privilege level for HLV(X)/HSV instructionsGeorg Kotheimer2021-03-231-11/+14
* target/riscv: flush TLB pages if PMP permission has been changedJim Shu2021-03-231-0/+4
* target/riscv: add log of PMP permission checkingJim Shu2021-03-231-0/+12
* target/riscv: propagate PMP permission to TLB pageJim Shu2021-03-233-43/+125
* target/riscv: fix vs() to return proper error codeFrank Chang2021-03-231-1/+1
* Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul...Peter Maydell2021-03-111-1/+1
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| * Various spelling fixesMichael Tokarev2021-03-091-1/+1
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