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* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-7/+16
* cpu: move do_unaligned_access to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-052-2/+2
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost2021-02-051-1/+1
* target/riscv: remove CONFIG_TCG, as it is always TCGClaudio Fontana2021-02-051-2/+1Star
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...Peter Maydell2021-01-184-1/+58
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| * riscv: Add semihosting supportKeith Packard2021-01-184-1/+58
* | target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng2021-01-163-264/+58Star
* | target/riscv: Add CSR name in the CSR function tableBin Meng2021-01-162-84/+249
* | target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng2021-01-162-9/+9
* | target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra2021-01-163-2/+8
* | gdb: riscv: Add target descriptionSylvain Pelissier2021-01-161-0/+13
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* tcg: Make tb arg to synchronize_from_tb constRichard Henderson2021-01-071-1/+2
* target/riscv: cpu: Set XLEN independently from targetAlistair Francis2020-12-181-9/+16
* target/riscv: csr: Remove compile time XLEN checksAlistair Francis2020-12-182-88/+92
* target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis2020-12-181-5/+7
* target/riscv: cpu: Remove compile time XLEN checksAlistair Francis2020-12-181-9/+10
* target/riscv: Specify the XLEN for CPUsAlistair Francis2020-12-181-10/+23
* target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis2020-12-182-0/+11
* target/riscv: fpu_helper: Match function defs in HELPER macrosAlistair Francis2020-12-182-24/+8Star
* target/riscv: Add a TYPE_RISCV_CPU_BASE CPUAlistair Francis2020-12-181-0/+6
* target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSRAlex Richardson2020-12-181-2/+2
* target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang2020-12-181-1/+2
* hmp: Pass monitor to mon_get_cpu_env()Kevin Wolf2020-11-131-1/+1
* target/riscv: Split the Hypervisor execute load helpersAlistair Francis2020-11-103-42/+17Star
* target/riscv: Remove the hyp load and store functionsAlistair Francis2020-11-105-166/+59Star
* target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis2020-11-104-51/+25Star
* target/riscv: Set the virtualised MMU mode when doing hyp accessesAlistair Francis2020-11-101-13/+17
* target/riscv: Add a virtualised MMU ModeAlistair Francis2020-11-103-3/+14
* target/riscv/csr.c : add space before the open parenthesis '('Xinhao Zhang2020-11-031-1/+1
* target/riscv: Add V extension state descriptionYifei Jiang2020-11-031-0/+25
* target/riscv: Add H extension state descriptionYifei Jiang2020-11-031-0/+47
* target/riscv: Add PMP state descriptionYifei Jiang2020-11-033-11/+70
* target/riscv: Add basic vmstate description of CPUYifei Jiang2020-11-034-8/+81
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-036-74/+41Star
* target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang2020-10-222-12/+34
* target/riscv: Fix implementation of HLVX.WU instructionGeorg Kotheimer2020-10-221-3/+3
* target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interruptGeorg Kotheimer2020-10-221-1/+3
* target/riscv: Fix update of hstatus.SPVPGeorg Kotheimer2020-10-221-1/+1
* riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis2020-10-222-2/+7
* icount: rename functions to be consistent with the module nameClaudio Fontana2020-10-051-2/+2
* cpu-timers, icount: new modulesClaudio Fontana2020-10-051-2/+2
* qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi2020-09-231-1/+1
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
* target/riscv: Set instance_align on RISCVCPU TypeInfoRichard Henderson2020-09-181-0/+1
* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell2020-09-134-12/+27
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