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* target/riscv: fix counter-enable checks in ctr()Xi Wang2019-02-121-3/+9
* RISC-V: Add misa runtime write supportMichael Clark2019-02-124-3/+68
* RISC-V: Add misa.MAFD checks to translateMichael Clark2019-02-121-0/+158
* RISC-V: Add misa to DisasContextMichael Clark2019-02-121-35/+40
* RISC-V: Add priv_ver to DisasContextAlistair Francis2019-02-121-2/+5
* RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark2019-02-125-37/+36Star
* RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark2019-02-122-8/+34
* RISC-V: Mark mstatus.fs dirtyRichard Henderson2019-02-122-13/+39
* RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson2019-02-122-8/+8
* RISC-V: Implement existential predicates for CSRsMichael Clark2019-01-094-79/+105
* RISC-V: Implement atomic mip/sip CSR updatesMichael Clark2019-01-091-28/+28
* RISC-V: Implement modular CSR helper interfaceMichael Clark2019-01-086-606/+904
* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1'...Peter Maydell2019-01-033-11/+13
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| * riscv/cpu: use device_class_set_parent_realizeMao Zhongyi2018-12-201-2/+2
| * target/riscv/pmp.c: Fix pmp_decode_napot()Anup Patel2018-12-201-1/+1
| * RISC-V: Add hartid and \n to interrupt loggingMichael Clark2018-12-201-8/+10
* | Clean up includesMarkus Armbruster2018-12-201-1/+0Star
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* RISC-V: Respect fences for user-only emulatorsPalmer Dabbelt2018-11-141-2/+0Star
* target/riscv: Fix sfence.vm/a both available in any priv versionBastian Koppelmann2018-11-141-5/+13
* target/riscv: Fix FCLASS_D being treated as RV64 onlyBastian Koppelmann2018-11-141-1/+3
* target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64Dayeol Lee2018-10-301-1/+1
* RISC-V: Update CSR and interrupt definitionsMichael Clark2018-10-173-321/+370
* RISC-V: Move non-ops from op_helper to cpu_helperMichael Clark2018-10-173-36/+35Star
* RISC-V: Allow setting and clearing multiple irqsMichael Clark2018-10-172-18/+28
* riscv: remove define cpu_init()Igor Mammedov2018-09-051-1/+0Star
* target/riscv: call gen_goto_tb on DISAS_TOO_MANYEmilio G. Cota2018-09-051-6/+1Star
* target/riscv: optimize indirect branchesEmilio G. Cota2018-09-051-1/+1
* target/riscv: optimize cross-page direct jumps in softmmuEmilio G. Cota2018-09-051-1/+1
* RISC-V: Simplify riscv_cpu_local_irqs_pendingMichael Clark2018-09-041-22/+12Star
* RISC-V: Improve page table walker spec complianceMichael Clark2018-09-042-21/+45
* RISC-V: Update address bits to support sv39 and sv48Michael Clark2018-09-041-4/+4
* RISC-V: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé2018-06-081-2/+4
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-10/+10
* Make address_space_translate{, _cached}() take a MemTxAttrs argumentPeter Maydell2018-05-311-1/+1
* target/riscv: Honor CPU_DUMP_FPURichard Henderson2018-05-181-5/+7
* target/riscv: Remove floatX_maybe_silence_nan from conversionsRichard Henderson2018-05-181-4/+2Star
* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...Peter Maydell2018-05-111-49/+17Star
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| * target/riscv: Use new atomic min/max expandersRichard Henderson2018-05-101-49/+17Star
* | target/riscv: convert to TranslatorOpsEmilio G. Cota2018-05-091-78/+80
* | target/riscv: convert to DisasContextBaseEmilio G. Cota2018-05-091-65/+64Star
* | target/riscv: convert to DisasJumpTypeEmilio G. Cota2018-05-091-44/+28Star
* | target/riscv: avoid integer overflow in next_page PC checkEmilio G. Cota2018-05-091-3/+3
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* RISC-V: No traps on writes to misa,minstret,mcycleMichael Clark2018-05-061-12/+13
* RISC-V: Make mtvec/stvec ignore vectored trapsMichael Clark2018-05-061-6/+8
* RISC-V: Add mcycle/minstret support for -icount autoMichael Clark2018-05-062-2/+28
* RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10Michael Clark2018-05-062-18/+50
* RISC-V: Allow S-mode mxr access when priv ISA >= v1.10Michael Clark2018-05-061-2/+5
* RISC-V: Clear mtval/stval on exceptions without infoMichael Clark2018-05-061-0/+8
* RISC-V: Hardwire satp to 0 for no-mmu caseMichael Clark2018-05-061-2/+5
* RISC-V: Update E and I extension orderMichael Clark2018-05-062-1/+2
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