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* Remove qemu-common.h include from most unitsMarc-André Lureau2022-04-061-1/+0Star
* Move CPU softfloat unions to cpu-float.hMarc-André Lureau2022-04-061-1/+1
* Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2022-04-062-3/+3
* target/riscv: rvv: Add missing early exit condition for whole register load/s...Yueh-Ting (eop) Chen2022-04-011-0/+5
* target/riscv: Avoid leaking "no translation" TLB entriesPalmer Dabbelt2022-04-011-6/+8
* target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé2022-03-061-1/+1
* target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2022-03-061-3/+1Star
* target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé2022-03-061-3/+2Star
* target: Include missing 'cpu.h'Philippe Mathieu-Daudé2022-03-061-0/+2
* misc: Add missing "sysemu/cpu-timers.h" includePhilippe Mathieu-Daudé2022-03-061-0/+1
* target/riscv: expose zfinx, zdinx, zhinx{min} propertiesWeiwei Li2022-03-031-0/+5
* target/riscv: add support for zhinx/zhinxminWeiwei Li2022-03-034-143/+296
* target/riscv: add support for zdinxWeiwei Li2022-03-032-78/+259
* target/riscv: add support for zfinxWeiwei Li2022-03-035-145/+369
* target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li2022-03-033-6/+29
* target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li2022-03-032-0/+16
* target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich2022-03-031-4/+4
* target: Add missing "qemu/timer.h" includePhilippe Mathieu-Daudé2022-02-211-0/+1
* target/riscv: add support for svpbmt extensionWeiwei Li2022-02-163-1/+6
* target/riscv: add support for svinval extensionWeiwei Li2022-02-165-0/+85
* target/riscv: add support for svnapot extensionWeiwei Li2022-02-163-3/+18
* target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li2022-02-161-0/+3
* target/riscv: Ignore reserved bits in PTE for RV64Guo Ren2022-02-163-1/+30
* target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel2022-02-162-0/+6
* target/riscv: Implement AIA IMSIC interface CSRsAnup Patel2022-02-161-0/+203
* target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel2022-02-163-0/+187
* target/riscv: Implement AIA mtopi, stopi, and vstopi CSRsAnup Patel2022-02-161-0/+156
* target/riscv: Implement AIA interrupt filtering CSRsAnup Patel2022-02-161-0/+23
* target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel2022-02-163-1/+131
* target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel2022-02-164-120/+474
* target/riscv: Implement AIA local interrupt prioritiesAnup Patel2022-02-164-21/+294
* target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel2022-02-162-0/+37
* target/riscv: Add defines for AIA CSRsAnup Patel2022-02-161-0/+119
* target/riscv: Add AIA cpu featureAnup Patel2022-02-161-1/+2
* target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel2022-02-162-8/+8
* target/riscv: Improve delivery of guest external interruptsAnup Patel2022-02-161-0/+13
* target/riscv: Implement hgeie and hgeip CSRsAnup Patel2022-02-166-38/+121
* target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel2022-02-163-8/+16
* target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-modeAnup Patel2022-02-161-1/+1
* target/riscv: Fix vill field write in vtypeLIU Zhiwei2022-02-161-0/+1
* target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich2022-02-166-0/+83
* target/riscv: iterate over a table of decodersPhilipp Tomsich2022-02-161-5/+27
* target/riscv: access cfg structure through DisasContextPhilipp Tomsich2022-02-161-4/+4
* target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich2022-02-164-69/+97
* target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptrPhilipp Tomsich2022-02-161-0/+2
* target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC...Philipp Tomsich2022-02-161-37/+41
* target/riscv: correct "code should not be reached" for x-rv128Frédéric Pétrot2022-02-162-2/+4
* target/riscv: Relax UXL field for debuggingLIU Zhiwei2022-01-211-4/+4
* target/riscv: Enable uxl field writeLIU Zhiwei2022-01-212-6/+25
* target/riscv: Set default XLEN for hypervisorLIU Zhiwei2022-01-211-0/+10
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