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* i386: tcg: remove inline from cpu_load_eflagsClaudio Fontana2020-12-162-13/+15
| | | | | | | | | | make it a regular function. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-9-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: move TCG cpu class initialization to tcg/Claudio Fontana2020-12-1619-148/+238
| | | | | | | | | | | | | | | | | | to do this, we need to take code out of cpu.c and helper.c, and also move some prototypes from cpu.h, for code that is needed in tcg/xxx_helper.c, and which in turn is part of the callbacks registered by the class initialization. Therefore, do some shuffling of the parts of cpu.h that are only relevant for tcg/, and put them in tcg/helper-tcg.h For FT0 and similar macros, put them in tcg/fpu-helper.c since they are used only there. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-8-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* x86/cpu: Add AVX512_FP16 cpu featureCathy Zhang2020-12-162-1/+3
| | | | | | | | | | | | | | AVX512 Half-precision floating point (FP16) has better performance compared to FP32 if the presicion or magnitude requirements are met. It's defined as CPUID.(EAX=7,ECX=0):EDX[bit 23]. Refer to https://software.intel.com/content/www/us/en/develop/download/\ intel-architecture-instruction-set-extensions-programming-reference.html Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Message-Id: <20201216224002.32677-1-cathy.zhang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: move hyperv_limits initialization to x86_cpu_realizefn()Vitaly Kuznetsov2020-12-163-1/+18
| | | | | | | | | As a preparation to expanding Hyper-V CPU features early, move hyperv_limits initialization to x86_cpu_realizefn(). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-5-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: move hyperv_version_id initialization to x86_cpu_realizefn()Vitaly Kuznetsov2020-12-163-2/+17
| | | | | | | | | As a preparation to expanding Hyper-V CPU features early, move hyperv_version_id initialization to x86_cpu_realizefn(). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-4-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: move hyperv_interface_id initialization to x86_cpu_realizefn()Vitaly Kuznetsov2020-12-163-6/+19
| | | | | | | | | As a preparation to expanding Hyper-V CPU features early, move hyperv_interface_id initialization to x86_cpu_realizefn(). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-3-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()Vitaly Kuznetsov2020-12-163-17/+34
| | | | | | | | | | | As a preparation to expanding Hyper-V CPU features early, move hyperv_vendor_id initialization to x86_cpu_realizefn(). Introduce x86_cpu_hyperv_realize() to not not pollute x86_cpu_realizefn() itself. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20201119103221.1665171-2-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: move cpu dump out of helper.c into cpu-dump.cClaudio Fontana2020-12-164-514/+539
| | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-7-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: move TCG accel files into tcg/Claudio Fontana2020-12-1616-13/+14
| | | | | | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: moved cc_helper_template.h to tcg/ too] Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20201212155530.23098-6-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: move hax accel files into hax/Claudio Fontana2020-12-1612-10/+11
| | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-4-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: move whpx accel files into whpx/Claudio Fontana2020-12-167-5/+6
| | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-3-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: move kvm accel files into kvm/Claudio Fontana2020-12-1616-14/+17
| | | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-2-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2020-12-155-4/+70
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20201215' into staging target-arm queue: * gdbstub: Correct misparsing of vCont C/S requests * openrisc: Move pic_cpu code into CPU object proper * nios2: Move IIC code into CPU object proper * Improve reporting of ROM overlap errors * xlnx-versal: Add USB support * hw/misc/zynq_slcr: Avoid #DIV/0! error * Numonyx: Fix dummy cycles and check for SPI mode on cmds # gpg: Signature made Tue 15 Dec 2020 13:59:46 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20201215: hw/block/m25p80: Fix Numonyx fast read dummy cycle count hw/block/m25p80: Check SPI mode before running some Numonyx commands hw/block/m25p80: Fix when VCFG XIP bit is set for Numonyx hw/block/m25p80: Make Numonyx config field names more accurate hw/misc/zynq_slcr: Avoid #DIV/0! error arm: xlnx-versal: Connect usb to virt-versal usb: xlnx-usb-subsystem: Add xilinx usb subsystem usb: Add DWC3 model usb: Add versal-usb2-ctrl-regs module elf_ops.h: Be more verbose with ROM blob names elf_ops.h: Don't truncate name of the ROM blobs we create hw/core/loader.c: Improve reporting of ROM overlap errors hw/core/loader.c: Track last-seen ROM in rom_check_and_register_reset() target/nios2: Use deposit32() to update ipending register target/nios2: Move nios2_check_interrupts() into target/nios2 target/nios2: Move IIC code into CPU object proper target/openrisc: Move pic_cpu code into CPU object proper hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y" hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs gdbstub: Correct misparsing of vCont C/S requests Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/nios2: Use deposit32() to update ipending registerPeter Maydell2020-12-151-2/+1Star
| | | | | | | | | | | | | | | | | | In nios2_cpu_set_irq(), use deposit32() rather than raw shift-and-mask operations to set the appropriate bit in the ipending register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201129174022.26530-4-peter.maydell@linaro.org
| * target/nios2: Move nios2_check_interrupts() into target/nios2Peter Maydell2020-12-152-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function nios2_check_interrupts)() looks only at CPU-internal state; it belongs in target/nios2, not hw/nios2. Move it into the same file as its only caller, so it can just be local to that file. This removes the only remaining code from cpu_pic.c, so we can delete that file entirely. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201129174022.26530-3-peter.maydell@linaro.org Reviewed-by: Wentong Wu <wentong.wu@intel.com> Tested-by: Wentong Wu <wentong.wu@intel.com>
| * target/nios2: Move IIC code into CPU object properPeter Maydell2020-12-152-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Nios2 architecture supports two different interrupt controller options: * The IIC (Internal Interrupt Controller) is part of the CPU itself; it has 32 IRQ input lines and no NMI support. Interrupt status is queried and controlled via the CPU's ipending and istatus registers. * The EIC (External Interrupt Controller) interface allows the CPU to connect to an external interrupt controller. The interface allows the interrupt controller to present a packet of information containing: - handler address - interrupt level - register set - NMI mode QEMU does not model an EIC currently. We do model the IIC, but its implementation is split across code in hw/nios2/cpu_pic.c and hw/intc/nios2_iic.c. The code in those two files has no state of its own -- the IIC state is in the Nios2CPU state struct. Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, so we can implement the IIC directly in the CPU object the same way that real hardware does. Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the only user of the IIC wire up directly to those instead. Note that the old code had an "NMI" concept which was entirely unused and also as far as I can see not architecturally correct, since only the EIC has a concept of an NMI. This fixes a Coverity-reported trivial memory leak of the IRQ array allocated in nios2_cpu_pic_init(). Fixes: Coverity CID 1421916 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201129174022.26530-2-peter.maydell@linaro.org Reviewed-by: Wentong Wu <wentong.wu@intel.com> Tested-by: Wentong Wu <wentong.wu@intel.com>
| * target/openrisc: Move pic_cpu code into CPU object properPeter Maydell2020-12-152-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The openrisc code uses an old style of interrupt handling, where a separate standalone set of qemu_irqs invoke a function openrisc_pic_cpu_handler() which signals the interrupt to the CPU proper by directly calling cpu_interrupt() and cpu_reset_interrupt(). Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, and the neater modern way to implement this is to simply have the CPU object itself provide the input IRQ lines. Create GPIO inputs to the OpenRISC CPU object, and make the only user of cpu_openrisc_pic_init() wire up directly to those instead. This allows us to delete the hw/openrisc/pic_cpu.c file entirely. This fixes a trivial memory leak reported by Coverity of the IRQs allocated in cpu_openrisc_pic_init(). Fixes: Coverity CID 1421934 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stafford Horne <shorne@gmail.com> Message-id: 20201127225127.14770-4-peter.maydell@linaro.org
* | Merge remote-tracking branch ↵Peter Maydell2020-12-153-34/+28Star
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine queue, 2020-12-15 * qdev code cleanup * Convert some QOM instance properties to class properties * Update git URLs on MAINTAINERS # gpg: Signature made Tue 15 Dec 2020 15:18:47 GMT # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: (25 commits) MAINTAINERS: Update my git repository URLs qdev: Move UUID property to qdev-properties-system.c qdev: Make qdev_propinfo_get_uint16() static qdev: Make error_set_from_qdev_prop_error() get Object* argument qdev: Make check_prop_still_unset() get Object* argument qdev: Make qdev_find_global_prop() get Object* argument qdev: Make qdev_get_prop_ptr() get Object* arg qdev: Make bit_prop_set() get Object* argument qdev: Make PropertyInfo.print method get Object* argument qdev: Don't use dev->id on set_size32() error message sparc: Check dev->realized at sparc_set_nwindows() qdev: Check dev->realized at set_size() qdev: Move property code to qdev-properties.[ch] cpu: Move cpu_common_props to hw/core/cpu.c cs4231: Get rid of empty property array netfilter: Use class properties netfilter: Reorder functions can_host: Use class properties arm/cpu64: Register "aarch64" as class property virt: Register "its" as class property ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * sparc: Check dev->realized at sparc_set_nwindows()Eduardo Habkost2020-12-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | sparc_set_nwindows() is one of the very few property setters that don't check dev->realized, and there's no reason for it to be special. Check dev->realized like the other setters. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20201211220529.2290218-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * arm/cpu64: Register "aarch64" as class propertyEduardo Habkost2020-12-151-10/+6Star
| | | | | | | | | | | | | | | | | | | | Class properties make QOM introspection simpler and easier, as they don't require an object to be instantiated. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20201111183823.283752-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: Register feature bit properties as class propertiesEduardo Habkost2020-12-151-24/+16Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Class properties make QOM introspection simpler and easier, as they don't require an object to be instantiated. Also, the hundreds of instance properties were having an impact on QMP commands that create temporary CPU objects. On my machine, run time of qmp_query_cpu_definitions() changed from ~200ms to ~16ms after applying this patch. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20201111183823.283752-5-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* | Merge remote-tracking branch ↵Peter Maydell2020-12-141-3/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging Pull request trivial-patches 20201214 # gpg: Signature made Mon 14 Dec 2020 15:52:07 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.0-pull-request: configure / meson: Move check for linux/btrfs.h to meson.build configure / meson: Move check for sys/kcov.h to meson.build configure / meson: Move check for sys/signal.h to meson.build configure / meson: Move check for drm.h to meson.build configure / meson: Move check for pty.h to meson.build configure: Remove the obsolete check for ifaddrs.h blockdev: Fix a memleak in drive_backup_prepare() block/file-posix: fix a possible undefined behavior elf2dmp/pdb: Plug memleak in pdb_init_from_file elf2dmp/qemu_elf: Plug memleak in QEMU_Elf_init configure: Test if $make actually exists ads7846: moves from the hw/display folder to the hw/input folder. CODING_STYLE.rst: Be less strict about 80 character limit fsdev: open brace '{' following struct go on the same line hw/pci-host/pam: Replace magic number by PAM_REGIONS_COUNT definition hw/xen: Don't use '#' flag of printf format MAINTAINERS: update my email address qemu-options.hx: Fix minor issues in icount documentation target/i386: tracing: format length values as hex Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/i386: tracing: format length values as hexDov Murik2020-12-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Three trace events had a literal "0x" prefix but the 'len' values were formatted in decimal base. Keep the prefix and format the numbers as hex, as is usually the case for length of memory regions. Signed-off-by: Dov Murik <dovmurik@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201103100745.160409-1-dovmurik@linux.vnet.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | | Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20201213' into ↵Peter Maydell2020-12-1412-354/+408
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging MIPS patches queue . Allow executing MSA instructions on Loongson-3A4000 . Update Huacai Chen email address . Various cleanups: - unused headers removal - use definitions instead of magic values - remove dead code - avoid calling unused code . Various code movements CI jobs results: https://gitlab.com/philmd/qemu/-/pipelines/229120169 https://cirrus-ci.com/build/4857731557359616 # gpg: Signature made Sun 13 Dec 2020 20:18:52 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/mips-20201213: (26 commits) target/mips: Use FloatRoundMode enum for FCR31 modes conversion target/mips: Remove unused headers from fpu_helper.c target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn() target/mips: Move cpu definitions, reset() and realize() to cpu.c target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c target/mips: Extract cpu_supports*/cpu_set* translate.c hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit() hw/mips/malta: Do not initialize MT registers if MT ASE absent target/mips: Do not initialize MT registers if MT ASE absent target/mips: Introduce ase_mt_available() helper target/mips: Remove mips_def_t unused argument from mvp_init() target/mips: Remove unused headers from op_helper.c target/mips: Remove unused headers from translate.c hw/mips: Move address translation helpers to target/mips/ target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT() target/mips: Explicit Release 6 MMU types target/mips: Allow executing MSA instructions on Loongson-3A4000 target/mips: Also display exception names in user-mode target/mips: Remove unused headers from cp0_helper.c ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/mips: Use FloatRoundMode enum for FCR31 modes conversionPhilippe Mathieu-Daudé2020-12-132-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the FloatRoundMode enum type introduced in commit 3dede407cc6 ("softfloat: Name rounding mode enum") instead of 'unsigned int'. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201123204448.3260804-2-f4bug@amsat.org>
| * | target/mips: Remove unused headers from fpu_helper.cPhilippe Mathieu-Daudé2020-12-131-4/+0Star
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-4-f4bug@amsat.org>
| * | target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn()Philippe Mathieu-Daudé2020-12-131-12/+8Star
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-17-f4bug@amsat.org>
| * | target/mips: Move cpu definitions, reset() and realize() to cpu.cPhilippe Mathieu-Daudé2020-12-133-244/+243Star
| | | | | | | | | | | | | | | | | | | | | | | | Nothing TCG specific there, move to common cpu code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-16-f4bug@amsat.org>
| * | target/mips: Move mips_cpu_add_definition() from helper.c to cpu.cPhilippe Mathieu-Daudé2020-12-132-33/+33
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-10-f4bug@amsat.org>
| * | target/mips: Extract cpu_supports*/cpu_set* translate.cPhilippe Mathieu-Daudé2020-12-132-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move cpu_supports*() and cpu_set_exception_base() from translate.c to cpu.c. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-9-f4bug@amsat.org>
| * | target/mips: Do not initialize MT registers if MT ASE absentPhilippe Mathieu-Daudé2020-12-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not initialize MT-related config registers if the MT ASE is not present. As some functions access the 'mvp' structure, we still zero-allocate it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-4-f4bug@amsat.org>
| * | target/mips: Introduce ase_mt_available() helperPhilippe Mathieu-Daudé2020-12-135-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of accessing CP0_Config3 directly and checking the 'Multi-Threading Present' bit, introduce an helper to simplify code review. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-3-f4bug@amsat.org>
| * | target/mips: Remove mips_def_t unused argument from mvp_init()Philippe Mathieu-Daudé2020-12-132-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mvp_init() doesn't require any CPU definition (beside the information accessible via CPUMIPSState). Remove the unused argument. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-2-f4bug@amsat.org>
| * | target/mips: Remove unused headers from op_helper.cPhilippe Mathieu-Daudé2020-12-131-4/+0Star
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-6-f4bug@amsat.org>
| * | target/mips: Remove unused headers from translate.cPhilippe Mathieu-Daudé2020-12-131-2/+0Star
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-3-f4bug@amsat.org>
| * | hw/mips: Move address translation helpers to target/mips/Philippe Mathieu-Daudé2020-12-134-2/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Address translation is an architectural thing (not hardware related). Move the helpers from hw/ to target/. As physical address and KVM are specific to system mode emulation, restrict this file to softmmu, so it doesn't get compiled for user-mode emulation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-2-f4bug@amsat.org>
| * | target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argumentPhilippe Mathieu-Daudé2020-12-132-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce cpu_supports_isa() which takes a CPUMIPSState argument, more useful at runtime when the CPU is created (no need to call the extensive object_class_by_name()). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201207215257.4004222-3-f4bug@amsat.org>
| * | target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()Philippe Mathieu-Daudé2020-12-132-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | As cpu_supports_isa() / cpu_supports_cps_smp() take a 'cpu_type' name argument, rename them cpu_type_supports_FEAT(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201207215257.4004222-2-f4bug@amsat.org>
| * | target/mips: Explicit Release 6 MMU typesPhilippe Mathieu-Daudé2020-12-131-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | As of Release 6, MMU type 4 is assigned to "Dual Variable-Page-Size and Fixed-Page-Size TLBs" and type 2 to "Block Address Translation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201201132817.2863301-4-f4bug@amsat.org>
| * | target/mips: Allow executing MSA instructions on Loongson-3A4000Philippe Mathieu-Daudé2020-12-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE: https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html Commit af868995e1b correctly set the 'MSA present' bit of Config3 register, but forgot to allow the MSA instructions decoding in insn_flags, so executing them triggers a 'Reserved Instruction'. Fix by adding the ASE_MSA mask to insn_flags. Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Huacai Chen <chenhc@lemote.com> Message-Id: <20201130102228.2395100-1-f4bug@amsat.org>
| * | target/mips: Also display exception names in user-modePhilippe Mathieu-Daudé2020-12-131-11/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently MIPS exceptions are displayed as string in system-mode emulation, but as number in user-mode. Unify by extracting the current system-mode code as excp_name() and use that in user-mode. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201119160536.1980329-1-f4bug@amsat.org>
| * | target/mips: Remove unused headers from cp0_helper.cPhilippe Mathieu-Daudé2020-12-131-3/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unused headers and add missing "qemu/log.h" since qemu_log() is called. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-5-f4bug@amsat.org>
| * | target/mips: Do not include CP0 helpers in user-mode emulationPhilippe Mathieu-Daudé2020-12-132-5/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CP0 helpers are restricted to system-mode emulation. Do not intent do build cp0_helper.c in user-mode (this allows to simplify some #ifdef'ry). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Huacai Chen <chenhc@lemote.com> Message-Id: <20201109090422.2445166-3-f4bug@amsat.org>
| * | target/mips: Replace magic values by CP0PM_MASK or TARGET_PAGE_BITS_MINPhilippe Mathieu-Daudé2020-12-132-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace magic values related to page size: 12 -> TARGET_PAGE_BITS_MIN 13 -> CP0PM_MASK Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Huacai Chen <chenhc@lemote.com> Message-Id: <20201109090422.2445166-2-f4bug@amsat.org>
| * | target/mips: Include "exec/memattrs.h" in 'internal.h'Philippe Mathieu-Daudé2020-12-132-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | mips_cpu_do_transaction_failed() requires MemTxAttrs and MemTxResult declarations. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-8-f4bug@amsat.org>
| * | target/mips/kvm: Remove unused headersPhilippe Mathieu-Daudé2020-12-131-2/+0Star
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-7-f4bug@amsat.org>
| * | target/mips/kvm: Assert unreachable code is not usedPhilippe Mathieu-Daudé2020-12-131-6/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | This code must not be used outside of KVM. Abort if it is. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhc@lemote.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200429082916.10669-3-f4bug@amsat.org>
* | | target/ppc: Introduce an mmu_is_64bit() helperGreg Kurz2020-12-147-12/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Callers don't really need to know how 64-bit MMU model enums are computed. Hide this in a helper. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20201209173536.1437351-3-groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | | ppc/translate: Use POWERPC_MMU_64 to detect 64-bit MMU modelsStephane Duverger2020-12-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ppc_tr_init_disas_context() function currently checks whether the MMU is 64-bit by ANDing its model type with POWERPC_MMU_64B. This is wrong : POWERPC_MMU_64B isn't a mask, it is the generic MMU model for pre-PowerISA-2.03 64-bit CPUs (ie. PowerPC 970 in QEMU). Use POWERPC_MMU_64 instead of POWERPC_MMU_64B. This should fix a potential bug with some 32-bit CPUs for which 'need_access_type' was mis-computed because (POWERPC_MMU_32B & POWERPC_MMU_64B) happens to be equal to 1. The end result being a crash in ppc_hash32_direct_store() because the access type isn't set: cpu_abort(cs, "ERROR: instruction should not need " "address translation\n"); This doesn't change anything for 'lazy_tlb_flush' since POWERPC_MMU_32B is checked first. Fixes: 5f2a6254522b ("ppc: Don't set access_type on all load/stores on hash64") Signed-off-by: Stephane Duverger <stephane.duverger@free.fr> [groug: - extended patch to address another misuse of POWERPC_MMU_64B - updated title and changelog accordingly] Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20201209173536.1437351-2-groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | | target/ppc: Remove "compat" property of server class POWER CPUsGreg Kurz2020-12-141-59/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This property has been deprecated since QEMU 5.0 by commit 22062e54bb68. We only kept a legacy hack that internally converts "compat" into the official "max-cpu-compat" property of the pseries machine type. According to our deprecation policy, we could have removed it for QEMU 5.2 already. Do it now ; since ppc_cpu_parse_featurestr() now just calls the generic parent_parse_features handler, drop it as well. Users are supposed to use the "max-cpu-compat" property of the pseries machine type instead. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20201201131103.897430-1-groug@kaod.org> Reviewed-by: Ján Tomko <jtomko@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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