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* tcg/tci: Implement clz, ctz, ctpopRichard Henderson2021-06-192-6/+15
* tcg/tci: Implement extract, sextractRichard Henderson2021-06-192-4/+36
* tcg/tci: Implement andc, orc, eqv, nand, norRichard Henderson2021-06-191-10/+10
* tcg/tci: Implement movcondRichard Henderson2021-06-192-5/+9
* tcg/tci: Implement goto_ptrRichard Henderson2021-06-193-1/+18
* tcg/tci: Change encoding to uint32_t unitsRichard Henderson2021-06-193-224/+176Star
* tcg/tci: Emit setcond before brcondRichard Henderson2021-06-191-34/+18Star
* tcg/tci: Reserve r13 for a temporaryRichard Henderson2021-06-192-0/+2
* tcg/tci: Use ffi for callsRichard Henderson2021-06-192-27/+25Star
* tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_orderRichard Henderson2021-06-191-2/+2
* tcg/tci: Improve tcg_target_call_clobber_regsRichard Henderson2021-06-191-2/+8
* tcg: Move MAX_CODE_GEN_BUFFER_SIZE to tcg-target.hRichard Henderson2021-06-111-0/+1
* tcg: Change parameters for tcg_target_const_matchRichard Henderson2021-06-041-4/+2Star
* tcg: Fix prototypes for tcg_out_vec_op and tcg_out_opMiroslav Rezanina2021-03-171-2/+3
* tcg/tci: Split out tcg_out_op_r[iI]Richard Henderson2021-03-171-15/+35
* tcg/tci: Split out tcg_out_op_vRichard Henderson2021-03-171-4/+10
* tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm}Richard Henderson2021-03-171-17/+53
* tcg/tci: Split out tcg_out_op_rrrrclRichard Henderson2021-03-171-8/+19
* tcg/tci: Split out tcg_out_op_rrrrRichard Henderson2021-03-171-6/+15
* tcg/tci: Split out tcg_out_op_rrrrrrRichard Henderson2021-03-171-8/+19
* tcg/tci: Split out tcg_out_op_rrclRichard Henderson2021-03-171-6/+15
* tcg/tci: Split out tcg_out_op_rrrbbRichard Henderson2021-03-171-7/+16
* tcg/tci: Split out tcg_out_op_rrrrrcRichard Henderson2021-03-171-9/+21
* tcg/tci: Split out tcg_out_op_rrrcRichard Henderson2021-03-171-6/+15
* tcg/tci: Split out tcg_out_op_rrrRichard Henderson2021-03-171-5/+14
* tcg/tci: Split out tcg_out_op_rrRichard Henderson2021-03-171-13/+23
* tcg/tci: Split out tcg_out_op_pRichard Henderson2021-03-171-6/+12
* tcg/tci: Split out tcg_out_op_lRichard Henderson2021-03-171-3/+11
* tcg/tci: Split out tcg_out_op_rrsRichard Henderson2021-03-171-43/+37Star
* tcg/tci: Push opcode emit into each caseRichard Henderson2021-03-171-3/+32
* tcg/tci: Remove tci_disasRichard Henderson2021-03-172-12/+0Star
* tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bitsRichard Henderson2021-03-171-2/+2
* tcg/tci: Clean up deposit operationsRichard Henderson2021-03-172-11/+14
* tcg/tci: Reuse tci_args_l for goto_tbRichard Henderson2021-03-172-18/+6Star
* tcg/tci: Reuse tci_args_l for exit_tbRichard Henderson2021-03-171-1/+1
* tcg/tci: Merge identical cases in generation (load/store opcodes)Richard Henderson2021-03-061-35/+14Star
* tcg/tci: Merge identical cases in generation (conditional opcodes)Richard Henderson2021-03-061-17/+6Star
* tcg/tci: Merge identical cases in generation (deposit opcode)Richard Henderson2021-03-061-10/+2Star
* tcg/tci: Merge identical cases in generation (exchange opcodes)Richard Henderson2021-03-061-21/+14Star
* tcg/tci: Merge identical cases in generation (arithmetic opcodes)Richard Henderson2021-03-061-48/+37Star
* tcg/tci: Remove TCG_CONSTRichard Henderson2021-02-053-72/+22Star
* tcg/tci: Fix TCG_REG_R4 misusageRichard Henderson2021-02-051-6/+1Star
* tcg/tci: Restrict TCG_TARGET_NB_REGS to 16Richard Henderson2021-02-052-53/+5Star
* tcg/tci: Implement 64-bit divisionRichard Henderson2021-02-052-8/+6Star
* tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*Richard Henderson2021-02-051-8/+0Star
* tcg/tci: Move stack bounds check to compile-timeRichard Henderson2021-02-051-0/+13
* tcg: Remove TCG_TARGET_CON_SET_HRichard Henderson2021-02-021-2/+0Star
* tcg/tci: Split out constraint sets to tcg-target-con-set.hRichard Henderson2021-02-023-142/+158
* tcg: Remove TCG_TARGET_CON_STR_HRichard Henderson2021-02-021-2/+0Star
* tcg/tci: Split out target constraints to tcg-target-con-str.hRichard Henderson2021-02-023-14/+13Star