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* clk: samsung: Change signature of exynos5_subcmus_init() functionSylwester Nawrocki2019-08-081-1/+6
| | | | | | | | | | | | | In order to make it easier in subsequent patch to create different subcmu lists for exynos5420 and exynos5800 SoCs the code is rewritten so we pass an array of pointers to the subcmus initialization function. Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver") Tested-by: Jaafar Ali <jaafarkhalaf@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lkml.kernel.org/r/20190808144929.18685-1-s.nawrocki@samsung.com Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: samsung: exynos5250: Use generic helper for handling suspend/resumeMarek Szyprowski2018-10-051-40/+2Star
| | | | | | | | | | | Replace common suspend/resume handling code by generic helper. Almost no functional change, the only difference is in handling of hypothetical memory allocation failure on boot. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
* clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devicesMarek Szyprowski2018-03-141-0/+6
| | | | | | | | | | | | | | | | | | FIMC LITE SYSMMU devices are defined in exynos5250.dtsi, but clocks for them are not instantiated by Exynos5250 clock provider driver. Add needed definitions for those clocks to fix IOMMU probe failure: ERROR: could not get clock /soc/sysmmu@13c40000:sysmmu(0) exynos-sysmmu 13c40000.sysmmu: Failed to get device clock(s)! exynos-sysmmu: probe of 13c40000.sysmmu failed with error -38 ERROR: could not get clock /soc/sysmmu@13c50000:sysmmu(0) exynos-sysmmu 13c50000.sysmmu: Failed to get device clock(s)! exynos-sysmmu: probe of 13c50000.sysmmu failed with error -38 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Fixes: bfed1074f213 ("clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks") Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMUMarek Szyprowski2018-03-061-16/+35
| | | | | | | | | | | | | | Clocks related to DISP1 block require special handling for power domain turn on/off sequences. Till now this was handled by Exynos power domain driver, but that approach was limited only to some special cases. This patch moves handling of those operations to clock controller driver. This gives more flexibility and allows fine tune values of some clock-specific registers. This patch moves handling of those mentioned clocks to Exynos5 sub-CMU driver instantiated from Exynos5250 driver. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Add compile time PLL rate validatorsAndrzej Hajda2018-02-231-27/+27
| | | | | | | | | | | | | | | | | | | | Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. To avoid possible mistakes we can use compile time validation. The patch introduces such validators and expands all initializers with additional input frequency parameter, required to validate rates. Since S3C24xx PLLs requires different validators two new macros have been introduced to deal with it. Also, since PLLs 4502 and 4508 have different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE. As the patch adds only compile time validators it should not have impact on compiled code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5250: Fix PLL ratesAndrzej Hajda2018-02-231-4/+4
| | | | | | | | | | | | | | | | | | | | Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. If that is not the case, rate of the PLL's child clock might be set not as expected. For instance, if in the PLL rates table we have a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate will return 393216003. If we now attempt to set rate of a PLL's child divider clock to 393216000/2 its rate will be 131072001, rather than 196608000. That is, the divider will be set to 3 instead of 2, because 393216003/2 is greater than 196608000. To fix this issue declared rates are changed to exactly match rates generated by the PLL, as calculated from the P, M, S, K coefficients. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Remove clkdev alias support in Exynos5250 clk driverMarek Szyprowski2017-10-091-9/+9
| | | | | | | | | | All Exynos5250 boards have been fully converted to device-tree and use generic dt-based CPUfreq driver, so there is no need to create any clkdev aliases for the clocks. Drop all the code related to aliases handling. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5250: Move sleep init function to init sectionKrzysztof Kozlowski2016-06-021-2/+2
| | | | | | | | The exynos5250_clk_sleep_init() function can be moved to init section because it is referenced only from other init-level calls. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5250: Constify all clock initializersKrzysztof Kozlowski2016-06-021-10/+10
| | | | | | | All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Remove useless check for return value of samsung_clk_initKrzysztof Kozlowski2016-06-021-2/+1Star
| | | | | | | | | The samsung_clk_init() cannot return NULL. Either it returns allocated memory or it panics. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Remove CLK_IS_ROOTStephen Boyd2016-03-031-5/+5
| | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: samsung: exynos5250: Add DISP1 clocksTomeu Vizoso2015-10-231-1/+13
| | | | | | | | | | | | | | When the DISP1 power domain is powered off, there's two clocks that need to be temporarily reparented to OSC, and back to their original parents when the domain is powered on again. We expose these two clocks in the DT bindings so that the DT node of the power domain can reference them. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
* Merge branch 'v4.3-topic/clk-samsung' of ↵Michael Turquette2015-07-281-0/+31
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into clk-next
| * clk: exynos5250: add cpu clock configuration data and instantiate cpu clockThomas Abraham2015-07-241-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5250. Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> [b.zolnierkie: split exynos5250 support from the original patch] [b.zolnierkie: moved E5250_CPU_DIV[0,1] macros to clk-exynos5250.c] Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
* | clk: samsung: Properly include clk.h and clkdev.hStephen Boyd2015-07-201-2/+0Star
|/ | | | | | | | | | | | | | Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. The clkdev.h header isn't always used either, so remove it and add in slab.h where files were relying on it to include slab for them. Cc: Chanwoo Choi <cw00.choi@samsung.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: samsung: Make of_device_id array constKrzysztof Kozlowski2014-07-261-1/+1
| | | | | | | | | Array of struct of_device_id may be be const as expected by of_match_table field and of_find_matching_node_and_match() function. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: Register clk provider only after registering its all clocksSylwester Nawrocki2014-06-301-0/+2
| | | | | | | | | | Ensure the clock provider is not registered until after all its related clocks were created and are ready to use. Currently there are races possible and any (of_)clk_get() call right after a clock provider's clk_init_cb callback call may fail. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk/exynos5250: fix bit number for tv sysmmu clockRahul Sharma2014-06-301-1/+1
| | | | | | | | | Change bit from 2 to 9 for tv (mixer) sysmmu clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Reviewed-by: Sachin Kamat <sachin.kamat@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* Merge tag 'samsung-drivers-2' of ↵Olof Johansson2014-05-311-0/+35
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers Merge "Samsung 2nd drivers for 3.16" from Kukjin Kim: This is including fix exynos cpufreq driver compilation with ARCH_MULTIPLATFORM. Even though this is a work around, this is required for support exynos multiplatform for a while and will be updated in near future. This is based on tags/samsung-exynos. * tag 'samsung-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (24 commits) cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM ARM: EXYNOS: Enable multi-platform build support ARM: EXYNOS: Consolidate Kconfig entries ARM: EXYNOS: Add support for EXYNOS5410 SoC ARM: EXYNOS: Support secondary CPU boot of Exynos3250 ARM: EXYNOS: Add Exynos3250 SoC ID ARM: EXYNOS: Add 5800 SoC support ARM: EXYNOS: initial board support for exynos5260 SoC clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks cpufreq: exynos: Fix the compile error ARM: S3C24XX: move debug-macro.S into the common space ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro ARM: S3C24XX: trim down debug uart handling ARM: compressed/head.S: remove s3c24xx special case ARM: EXYNOS: Remove unnecessary inclusion of cpu.h ARM: EXYNOS: Migrate Exynos specific macros from plat to mach ARM: EXYNOS: Remove exynos_subsys registration ARM: EXYNOS: Remove duplicate lines in Makefile ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling ARM: dts: Remove g2d_pd node for exynos5420 ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocksCho KyongHo2014-05-251-0/+35
| | | | | | | | | | | | | | | | | | | | This patch adds the missing sysmmu clocks for Display and ISP blocks. Signed-off-by: Cho KyongHo <pullip.cho@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | ARM: EXYNOS: Move arm core power down clock to exynos5250 common clockAmit Daniel Kachhap2014-05-251-0/+42
|/ | | | | | | | | | | | | | | | | Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform. Cc: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsugn.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com> [t.figa: Rebased onto current kernel sources.] Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: samsung: exynos5250: Add clocks for G3DArun Kumar K2014-05-141-1/+14
| | | | | | | | | This patch adds the required clocks for ARM Mali IP in Exynos5250. Signed-off-by: Arun Kumar K <arun.kk@samsung.com> [t.figa: Changed clock ID to avoid conflict with CLK_SSS] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250/5420: Add gate clock for SSS moduleNaveen Krishna Chatradhi2014-05-141-0/+1
| | | | | | | | | This patch adds gating clock for SSS(Security SubSystem) module on Exynos5250/5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> [t.figa: Fixed sort order and group name.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk/samsung: add support for multiple clock providersRahul Sharma2014-05-141-10/+15
| | | | | | | | | | | | | | | | | | Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: Drop old suspend/resume codeTomasz Figa2014-02-141-1/+1
| | | | | | | | | | | | Since all SoC drivers have been moved to local suspend/resume handling, the old code can be safely dropped. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: samsung: exynos5250: Move suspend/resume handling to SoC driverTomasz Figa2014-02-141-5/+44
| | | | | | | | | | | | Since there are multiple differences in how suspend/resume of particular Exynos SoCs must be handled, SoC driver is better place for suspend/resume handlers and so this patch moves them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: exynos5250: add clock ID for div_pcm0Andrew Bresticker2014-01-081-1/+1
| | | | | | | | | | | | There is no gate for the PCM clock input to the AudioSS block, so the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that we can reference it in device trees. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos5250: replace clock ID private enums with IDs from DT headerAndrzej Hajda2014-01-081-295/+264Star
| | | | | | | | | | | The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos5250: register APLL rate tableAndrew Bresticker2014-01-081-1/+24
| | | | | | | | | Register the APLL rate table so that we can set the APLL rate from the cpufreq driver. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apllSachin Kamat2013-12-301-1/+2
| | | | | | | | | Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the clock rate in the cpufreq driver. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Fix parents of gate clocks from MFC domainTomasz Figa2013-12-301-3/+5
| | | | | | | | | This patch adds mout_aclk333_sub mux clock and updates gate clocks from MFC domain to have it as their parent as specified in SoC documentation. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Correct parent list of audio muxesTomasz Figa2013-12-301-3/+3
| | | | | | | | | | According to SoC documentation, input 5 of mout_audio muxes is connected to xxti (named fin_pll in the driver). This patch corrects defined parent arrays to match SoC documentation. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Add missing unpopulated mux parentsTomasz Figa2013-12-301-4/+12
| | | | | | | | | | | This patch updates mux parent arrays with unpopulated mux inputs, as all inputs need to be specified in parent arrays passed to clk_register_mux(), otherwise clk_set_parent() can generate out of bound accesses to the array. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domainTomasz Figa2013-12-301-6/+8
| | | | | | | | | This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC documentation is the correct parent of DISP1 gate clocks. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domainTomasz Figa2013-12-301-8/+17
| | | | | | | | | | This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions of GSCL domain gate clocks to use it as their parent, as specified in SoC documentation. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Make names of mux and div clocks consistentTomasz Figa2013-12-301-122/+123
| | | | | | | | | | This patch renames all mux clocks to start with mout_ prefix and all div clocks to start with div_ prefix for consistency with other clocks already defined this way. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Sort definitions by registers and bitfieldTomasz Figa2013-12-301-102/+188
| | | | | | | | | | | | | This patch reorders clock definitions, so they are sorted by register addresses and bitfield shifts. When at it, blank lines are added to separate definitions of clocks from different registers. Overall this should make the driver more readable and reduce the number of potential conflicts when adding new entries. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clockAbhilash Kesavan2013-12-301-1/+2
| | | | | | | | | | | | The sysreg (system register) generates control signals for various blocks like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused clock at boot-up. This can lead to failures in operation of above blocks, because they can not be configured properly if this clock is disabled. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Add MDMA0 clocksAbhilash Kesavan2013-12-301-1/+4
| | | | | | | | | | | Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure that the clock is enabled when MDMA0 is used on systems on which firmware gates the clockby default. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Fix ACP gate register offsetAbhilash Kesavan2013-12-301-1/+1
| | | | | | | | | | | | The CLK_GATE_IP_ACP register offset is incorrectly listed making definition of g2d clock incorrect, which may lead to system failures when trying to use G2D on systems on which firmware gates this clock by default. Fix this and the register ordering as well. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: exynos5250: fix sysmmu_mfc{l,r} gate clocksAndrew Bresticker2013-12-301-2/+2
| | | | | | | | | | | The gate clocks for the MFC sysmmus appear to be flipped, i.e. GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr. Fix this so that the MFC will start up. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Simplify registration of PLL rate tablesTomasz Figa2013-09-061-10/+2Star
| | | | | | | | | | | Since the _get_rate() helper has been modified to use __clk_lookup() internally, checking of PLL input rates can be done using it and so the registration code can be simplified. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystemRahul Sharma2013-08-291-2/+2
| | | | | | | | | parent of hdmi and mixer block is mentioned as aclk200 which is not correct. It is clocked by the ouput of aclk200_disp1. Hence parent for mixer and hdmi clocks is changed to aclk200_disp1. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: exynos5250: Fix incorrect placement of __initdataSachin Kamat2013-08-091-5/+5
| | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: exynos5250: Make exynos5250_plls staticSachin Kamat2013-08-091-1/+1
| | | | | | | exynos5250_plls is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoCVikas Sajjan2013-08-021-0/+38
| | | | | | | | Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: samsung: Reorder MUX registration for mout_vpllsrcVikas Sajjan2013-08-021-1/+6
| | | | | | | | | | | | | While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the "fout_vpll" (child), we found get rate was failing. So this patch moves the mout_vpllsrc MUX out of the existing common list and registers the mout_vpllsrc MUX before the PLL registrations. Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: samsung: Add support to register rate_table for samsung pllsYadwinder Singh Brar2013-08-021-7/+7
| | | | | | | | | | This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate. Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-06-06 18:50:41 +0200