summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/i915_reg.h
Commit message (Expand)AuthorAgeFilesLines
...
* drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICLJosé Roberto de Souza2018-10-061-2/+2
* drm/i915: Add plane alpha blending support, v2.Maarten Lankhorst2018-10-021-0/+2
* drm/i915/icl: Define TA_TIMING_PARAM registersMadhav Chauhan2018-09-261-0/+23
* drm/i915/icl: Define data/clock lanes dphy timing registersMadhav Chauhan2018-09-261-0/+58
* drm/i915: Clean up scaler setup, v2.Maarten Lankhorst2018-09-211-3/+4
* drm/i915/skl+: Decode memory bandwidth and parametersMahesh Kumar2018-09-131-0/+18
* drm/i915/bxt: Decode memory bandwidth and parametersMahesh Kumar2018-09-131-0/+30
* drm/i915/icl: Define T_INIT_MASTER registersMadhav Chauhan2018-09-111-0/+6
* drm/i915/icl: Fix context RPCS programmingTvrtko Ursulin2018-09-041-0/+2
* drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engineManasi Navare2018-08-291-2/+2
* drm/i915/icl: implement the tc/legacy HPD {dis,}connect flowsPaulo Zanoni2018-08-241-0/+6
* drm/i915: Rename PLANE_CTL_DECOMPRESSION_ENABLEDhinakaran Pandiyan2018-08-231-1/+1
* drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLLManasi Navare2018-08-201-0/+5
* drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separa...Manasi Navare2018-08-201-1/+4
* drm/i915: remove confusing GPIO vs PCH_GPIOLucas De Marchi2018-08-161-19/+5Star
* drm/i915: make PCH_GMBUS* definitions private to gvtLucas De Marchi2018-08-161-7/+0Star
* drm/i915: set DP Main Stream Attribute for color range on DDI platformsJani Nikula2018-08-141-0/+1
* drm/i915/icl: Add missing power gate enumsImre Deak2018-08-081-0/+2
* drm/i915: Use existing power well IDs where possibleImre Deak2018-08-081-3/+0Star
* drm/i915: Make power well ID names more uniformImre Deak2018-08-081-5/+5
* drm/i915: Remove redundant power well IDsImre Deak2018-08-081-105/+13Star
* drm/i915/ddi: Use power well CTL IDX instead of IDImre Deak2018-08-081-44/+84
* drm/i915/vlv: Use power well CTL IDX instead of IDImre Deak2018-08-081-5/+17
* drm/i915: Clear all residual RPS events on disabling interruptsChris Wilson2018-08-031-2/+4
* Revert "drm/i915/icl: WaEnableFloatBlendOptimization"Mika Kuoppala2018-08-011-3/+0Star
* drm/i915/icl: Set TBT IO in Aux transactionAnusha Srivatsa2018-07-281-0/+1
* drm/i915/icl: toggle PHY clock gating around link trainingPaulo Zanoni2018-07-251-0/+20
* drm/i915/icl: program MG_DP_MODEPaulo Zanoni2018-07-251-0/+15
* drm/i915/icl: Update FIA supported lane count for hpd.Animesh Manna2018-07-251-0/+3
* drm/i915/icl: implement icl_digital_port_connected()Paulo Zanoni2018-07-251-0/+8
* drm/i915/icl: Add remaining registers and bitfields for MG PHY DDIManasi Navare2018-07-251-113/+157
* drm/i915/dsc: Add missing _MMIO() from PPS registersAnusha Srivatsa2018-07-211-38/+38
* i915/dp/dsc: Add Rate Control Range Parameter RegistersAnusha Srivatsa2018-07-191-0/+104
* i915/dp/dsc: Add Rate Control Buffer Threshold RegistersAnusha Srivatsa2018-07-191-0/+51
* i915/dp/dsc: Add DSC PPS register definitionsAnusha Srivatsa2018-07-191-0/+255
* drm/i915/icl: Add VIDEO_DIP registersAnusha Srivatsa2018-07-191-0/+23
* drm/i915/gmbus: Enable burst readRamalingam C2018-07-121-0/+1
* drm/i915/gmbus: Increase the Bytes per Rd/Wr OpRamalingam C2018-07-121-0/+1
* drm/i915: use the ICL stolen memoryPaulo Zanoni2018-07-111-0/+1
* drm/i915/icl: Define AUX lane registers for Port A/BMadhav Chauhan2018-07-061-0/+23
* drm/i915/icl: Define PORT_CL_DW_10 registerMadhav Chauhan2018-07-061-0/+20
* drm/i915/icl: Define DSI mode ctl registerMadhav Chauhan2018-07-061-0/+8
* drm/i915/icl: Program DSI Escape clock DividerMadhav Chauhan2018-07-061-0/+1
* drm/i915/icl: Define register for DSI PLLMadhav Chauhan2018-07-051-0/+15
* drm/i915: Fix pre-ILK error interrupt ackVille Syrjälä2018-07-041-1/+0Star
* drm/i915/psr: Add psr1 live statusVathsala Nagaraju2018-07-021-0/+1
* drm/i915: abstract and document register picking macrosJani Nikula2018-07-021-6/+22
* drm/i915/icp: Add Interrupt SupportAnusha Srivatsa2018-06-271-1/+40
* drm/i915/icl: Add power well supportImre Deak2018-06-271-9/+69
* drm/i915/psr: Enable CRC check in the static frame on the sink sideJosé Roberto de Souza2018-06-271-0/+1
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-12 08:12:27 +0200