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path: root/drivers/gpu/drm/i915/intel_ddi.c
Commit message (Expand)AuthorAgeFilesLines
* drm/i915/ddi: switch to kernel typesJani Nikula2019-01-211-26/+26
* drm/i915: Pass down rc in intel_encoder->compute_config()Lyude Paul2019-01-161-3/+3
* drm/i915: Markup paired operations on display power domainsChris Wilson2019-01-141-14/+22
* drm/i915: avoid division by zero on skl_calc_wrpll_linkYoung Xiao2018-12-281-0/+3
* drm/i915: DDI: call intel_psr_ and _edp_drrs_enable() on pipe updates (v2)Hans de Goede2018-12-251-0/+19
* drm/i915/icl: Fix HPD handling for TypeC legacy portsImre Deak2018-12-181-7/+56
* drm/i915/icl: combo port vswing programming changes per BSPECClint Taylor2018-12-181-152/+86Star
* drm/i915/hdmi: SCDC Scrambling enable without CTS modeClint Taylor2018-12-111-3/+2Star
* drm/i915/icl: Add get config functionality for DSIVandita Kulkarni2018-12-031-2/+2
* drm/i915/icl: Sanitize DDI port clock gating for DSI portsImre Deak2018-12-031-17/+48
* drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooksJani Nikula2018-12-031-50/+34Star
* drm/i915/fec: Disable FEC state.Anusha Srivatsa2018-11-291-4/+24
* i915/dp/fec: Configure the Forward Error Correction bits.Anusha Srivatsa2018-11-291-0/+23
* drm/i915/fec: Set FEC_READY in FEC_CONFIGURATIONAnusha Srivatsa2018-11-291-0/+11
* drm/i915/dsc: Enable and disable appropriate power wells for VDSCManasi Navare2018-11-291-0/+6
* drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enablingManasi Navare2018-11-291-0/+2
* drm/i915/dp: Enable/Disable DSC in DP SinkGaurav K Singh2018-11-291-0/+5
* drm/i915: Make CHICKEN_TRANS reg not depend on enum valueImre Deak2018-11-211-12/+25
* drm/i915/bios: rename intel_aux_ch() to intel_bios_port_aux_ch()Jani Nikula2018-11-151-1/+1
* drm/i915/icl: Fix PLL mapping sanitization for DP portsImre Deak2018-11-091-2/+25
* drm/i915/ddi: Add more sanity check to the encoder HW readoutImre Deak2018-11-091-24/+52
* drm/i915/icl: Configure MG DP mode for HDMI ports tooImre Deak2018-11-051-1/+67
* drm/i915/icl: Configure MG PHY gating for HDMI ports tooImre Deak2018-11-051-0/+70
* drm/i915/icl+: Sanitize port to PLL mappingImre Deak2018-11-021-0/+23
* drm/i915: Enable AUX power for HDMI DDI/TypeC main link tooImre Deak2018-11-021-3/+9
* drm/i915: Enable AUX power earlierImre Deak2018-11-021-32/+34
* drm/i915: Use a helper to get the aux power domainImre Deak2018-11-021-1/+1
* drm/i915: Init aux_ch for HDMI ports tooImre Deak2018-11-021-0/+1
* drm/i915: Move aux_ch to intel_digital_portImre Deak2018-11-021-1/+3
* drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hookManasi Navare2018-11-011-0/+49
* drm/i915: compute_min_voltage_level sort platforms newer-to-olderRodrigo Vivi2018-10-221-3/+3
* drm/i915: ddi_clock_get sort platforms newer-to-older.Rodrigo Vivi2018-10-221-8/+8
* drm/i915/icl: Fix DDI/TC port clk_off bitsMahesh Kumar2018-10-161-3/+18
* drm/i915/icl: create function to identify combophy portMahesh Kumar2018-10-161-7/+8
* drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCONShashank Sharma2018-10-151-0/+7
* drm/i915: Add AVI infoframe support for LSPCONShashank Sharma2018-10-151-4/+15
* drm/i915: Add CRTC output format YCBCR 4:2:0Shashank Sharma2018-10-151-1/+1
* drm/i915: Apply correct ddi translation table for AML deviceLee, Shawn C2018-10-051-3/+3
* drm/i915: Get rid of crtc->config from icl_pll_to_ddi_pll_selMaarten Lankhorst2018-10-051-7/+8
* drm/i915: Pass intel_encoder to infoframe functionsVille Syrjälä2018-10-011-3/+3
* drm/i915: use for_each_pipe loop to assign crtc_maskMahesh Kumar2018-09-251-1/+3
* drm/i915/psr: Enable AUX-A IO power well on ICL for PSRDhinakaran Pandiyan2018-09-191-1/+1
* drm/i915: Fix ICL+ HDMI clock readoutVille Syrjälä2018-09-041-1/+1
* drm/i915/dp_mst: Fix enabling pipe clock for all streamsImre Deak2018-09-011-8/+9
* drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLLManasi Navare2018-08-201-2/+79
* drm/i915: set DP Main Stream Attribute for color range on DDI platformsJani Nikula2018-08-141-0/+4
* drm/i915/icl: toggle PHY clock gating around link trainingPaulo Zanoni2018-07-251-0/+3
* drm/i915/icl: program MG_DP_MODEPaulo Zanoni2018-07-251-0/+2
* drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDIManasi Navare2018-07-251-6/+129
* drm/i915: Nuke dev_priv->irq_port[]Ville Syrjälä2018-07-131-1/+0Star
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